I write VHDL code that make sine wave (sinewave.vhd). I also wirte Test Bench (sinewave_TB.vhd) to the sine wave code. After i "Analysis & Synthesis" the sinewave.vhd i click on the butten "RTL Simulation" and the ModelSim open but not run (don't view variables) the simulation (don't run the sinewave_TB.vhd). what is the problem?
Aviv Y. wrote: > and the ModelSim open but not run (don't view variables) the simulation > (don't run the sinewave_TB.vhd). Show a screenshot of your ModelSim.
Attached files:
I add a print screen of the ModelSim. waht is the problem?
Why do you have a second library called rtl_work? Where is the (compiled) testbench? Try the following commands in the window on the bottom (on the 'ModelSim>' prompt):
1 | vlib work |
2 | vcom sinewave.vhd |
3 | vcom sinewave_TB.vhd |
4 | vsim sinewave_TB |
5 | add wave * |
6 | run 100 ns |
Post the error messages, in case they appear. Rick
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