How to port map selected signals from a large vector to smaller one

Sorry, I mean to say din is of of size 16:

din : in STD_LOGIC_VECTOR (15 downto 0);

Rohan Narkhede wrote:
> I write the code :
>
> din=>(sumf(23 downto 20, 15 downto 12, 7 downto 0)).

while din is std_logic_vector (7 downto 0) is only 8 Bit wide, you cant 
put in 16 Bits!

Either you define din as std_logic_vector (15 downto 0) and try this:

[code] din <= sumf(23 downto 20) & sumf(15 downto 12) & sumf(7 downto 
0);

Or you have to serialize the signal an feed in two cycles.

Rohan Narkhede wrote:
> Sorry, I mean to say din is of of size 16:
>
> din : in STD_LOGIC_VECTOR (15 downto 0);

Sorry, i didnt read yout secon post...

I think, this should work:

1

 din <= sumf(23 downto 20) & sumf(15 downto 12) & sumf(7 downto 

2

0);