Hi, In verilog is it possible to create Variable memory ? Please,help me with solution. Please see the below Example code in the attachments After running the code (In the attachments), i got the below error ERROR:HDLCompiler:44 - "D:\Xilinx_Codes\Final_FE_and_BD_Synthesis_XILINX\Box_Counting\Box_Count ing\box_count.v" Line 137: append_max is not a constant ERROR:HDLCompiler:598 - "D:\Xilinx_Codes\Final_FE_and_BD_Synthesis_XILINX\Box_Counting\Box_Count ing\box_count.v" Line 21: Module <box_count> ignored due to previous errors. In the code. "append_max" is the variable which changes based on its dependable variables. Thanks in advance.
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Priya S. wrote: > Hi, In verilog is it possible to create Variable memory ? Please,help me > with solution. This is not possible, and the error message clearly states it.
Hi Lattice, Thank you very much for your kind response.
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