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Forum: FPGA, VHDL & Verilog ImplementationOpt Design[Opt 31-37] Multi-driver net found in the design


von Junior H. (Company: University) (junior_hpc)


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Hello. I have this working code.
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.std_logic_unsigned.all;
4
use ieee.numeric_std.all;
5
6
entity xillydemo is
7
  port (
8
    PCIE_PERST_B_LS : IN std_logic;
9
    PCIE_REFCLK_N : IN std_logic;
10
    PCIE_REFCLK_P : IN std_logic;
11
    PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
12
    PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
13
    GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
14
    PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
15
    PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));
16
end xillydemo;
17
18
architecture sample_arch of xillydemo is
19
  component xillybus
20
    port (
21
      PCIE_PERST_B_LS : IN std_logic;
22
      PCIE_REFCLK_N : IN std_logic;
23
      PCIE_REFCLK_P : IN std_logic;
24
      PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
25
      PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
26
      GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
27
      PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
28
      PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);
29
      bus_clk : OUT std_logic;
30
      quiesce : OUT std_logic;
31
      user_r_mem_8_rden : OUT std_logic;
32
      user_r_mem_8_empty : IN std_logic;
33
      user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
34
      user_r_mem_8_eof : IN std_logic;
35
      user_r_mem_8_open : OUT std_logic;
36
      user_w_mem_8_wren : OUT std_logic;
37
      user_w_mem_8_full : IN std_logic;
38
      user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
39
      user_w_mem_8_open : OUT std_logic;
40
      user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
41
      user_mem_8_addr_update : OUT std_logic;
42
      user_r_read_32_rden : OUT std_logic;
43
      user_r_read_32_empty : IN std_logic;
44
      user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
45
      user_r_read_32_eof : IN std_logic;
46
      user_r_read_32_open : OUT std_logic;
47
      user_r_read_8_rden : OUT std_logic;
48
      user_r_read_8_empty : IN std_logic;
49
      user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
50
      user_r_read_8_eof : IN std_logic;
51
      user_r_read_8_open : OUT std_logic;
52
      user_w_write_32_wren : OUT std_logic;
53
      user_w_write_32_full : IN std_logic;
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      user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
55
      user_w_write_32_open : OUT std_logic;
56
      user_w_write_8_wren : OUT std_logic;
57
      user_w_write_8_full : IN std_logic;
58
      user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
59
      user_w_write_8_open : OUT std_logic);
60
  end component;
61
62
  component fifo_8x2048
63
    port (
64
      clk: IN std_logic;
65
      srst: IN std_logic;
66
      din: IN std_logic_VECTOR(7 downto 0);
67
      wr_en: IN std_logic;
68
      rd_en: IN std_logic;
69
      dout: OUT std_logic_VECTOR(7 downto 0);
70
      full: OUT std_logic;
71
      empty: OUT std_logic);
72
  end component;
73
74
  component fifo_32x512
75
    port (
76
      clk: IN std_logic;
77
      srst: IN std_logic;
78
      din: IN std_logic_VECTOR(31 downto 0);
79
      wr_en: IN std_logic;
80
      rd_en: IN std_logic;
81
      dout: OUT std_logic_VECTOR(31 downto 0);
82
      full: OUT std_logic;
83
      empty: OUT std_logic);
84
  end component;
85
86
-- Synplicity black box declaration
87
  attribute syn_black_box : boolean;
88
  attribute syn_black_box of fifo_32x512: component is true;
89
  attribute syn_black_box of fifo_8x2048: component is true;
90
91
  type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
92
  signal demoarray : demo_mem;
93
  
94
  signal bus_clk :  std_logic;
95
  signal quiesce : std_logic;
96
97
  signal reset_8 : std_logic;
98
  signal reset_32 : std_logic;
99
100
  signal ram_addr : integer range 0 to 31;
101
  
102
  signal user_r_mem_8_rden :  std_logic;
103
  signal user_r_mem_8_empty :  std_logic;
104
  signal user_r_mem_8_data :  std_logic_vector(7 DOWNTO 0);
105
  signal user_r_mem_8_eof :  std_logic;
106
  signal user_r_mem_8_open :  std_logic;
107
  signal user_w_mem_8_wren :  std_logic;
108
  signal user_w_mem_8_full :  std_logic;
109
  signal user_w_mem_8_data :  std_logic_vector(7 DOWNTO 0);
110
  signal user_w_mem_8_open :  std_logic;
111
  signal user_mem_8_addr :  std_logic_vector(4 DOWNTO 0);
112
  signal user_mem_8_addr_update :  std_logic;
113
  signal user_r_read_32_rden :  std_logic;
114
  signal user_r_read_32_empty :  std_logic;
115
  signal user_r_read_32_data :  std_logic_vector(31 DOWNTO 0);
116
  signal user_r_read_32_eof :  std_logic;
117
  signal user_r_read_32_open :  std_logic;
118
  signal user_r_read_8_rden :  std_logic;
119
  signal user_r_read_8_empty :  std_logic;
120
  signal user_r_read_8_data :  std_logic_vector(7 DOWNTO 0);
121
  signal user_r_read_8_eof :  std_logic;
122
  signal user_r_read_8_open :  std_logic;
123
  signal user_w_write_32_wren :  std_logic;
124
  signal user_w_write_32_full :  std_logic;
125
  signal user_w_write_32_data :  std_logic_vector(31 DOWNTO 0);
126
  signal user_w_write_32_open :  std_logic;
127
  signal user_w_write_8_wren :  std_logic;
128
  signal user_w_write_8_full :  std_logic;
129
  signal user_w_write_8_data :  std_logic_vector(7 DOWNTO 0);
130
  signal user_w_write_8_open :  std_logic;
131
132
begin
133
  xillybus_ins : xillybus
134
    port map (
135
      -- Ports related to /dev/xillybus_mem_8
136
      -- FPGA to CPU signals:
137
      user_r_mem_8_rden => user_r_mem_8_rden,
138
      user_r_mem_8_empty => user_r_mem_8_empty,
139
      user_r_mem_8_data => user_r_mem_8_data,
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      user_r_mem_8_eof => user_r_mem_8_eof,
141
      user_r_mem_8_open => user_r_mem_8_open,
142
      -- CPU to FPGA signals:
143
      user_w_mem_8_wren => user_w_mem_8_wren,
144
      user_w_mem_8_full => user_w_mem_8_full,
145
      user_w_mem_8_data => user_w_mem_8_data,
146
      user_w_mem_8_open => user_w_mem_8_open,
147
      -- Address signals:
148
      user_mem_8_addr => user_mem_8_addr,
149
      user_mem_8_addr_update => user_mem_8_addr_update,
150
151
      -- Ports related to /dev/xillybus_read_32
152
      -- FPGA to CPU signals:
153
      user_r_read_32_rden => user_r_read_32_rden,
154
      user_r_read_32_empty => user_r_read_32_empty,
155
      user_r_read_32_data => user_r_read_32_data,
156
      user_r_read_32_eof => user_r_read_32_eof,
157
      user_r_read_32_open => user_r_read_32_open,
158
159
      -- Ports related to /dev/xillybus_read_8
160
      -- FPGA to CPU signals:
161
      user_r_read_8_rden => user_r_read_8_rden,
162
      user_r_read_8_empty => user_r_read_8_empty,
163
      user_r_read_8_data => user_r_read_8_data,
164
      user_r_read_8_eof => user_r_read_8_eof,
165
      user_r_read_8_open => user_r_read_8_open,
166
167
      -- Ports related to /dev/xillybus_write_32
168
      -- CPU to FPGA signals:
169
      user_w_write_32_wren => user_w_write_32_wren,
170
      user_w_write_32_full => user_w_write_32_full,
171
      user_w_write_32_data => user_w_write_32_data,
172
      user_w_write_32_open => user_w_write_32_open,
173
174
      -- Ports related to /dev/xillybus_write_8
175
      -- CPU to FPGA signals:
176
      user_w_write_8_wren => user_w_write_8_wren,
177
      user_w_write_8_full => user_w_write_8_full,
178
      user_w_write_8_data => user_w_write_8_data,
179
      user_w_write_8_open => user_w_write_8_open,
180
181
      -- General signals
182
      PCIE_PERST_B_LS => PCIE_PERST_B_LS,
183
      PCIE_REFCLK_N => PCIE_REFCLK_N,
184
      PCIE_REFCLK_P => PCIE_REFCLK_P,
185
      PCIE_RX_N => PCIE_RX_N,
186
      PCIE_RX_P => PCIE_RX_P,
187
      GPIO_LED => GPIO_LED,
188
      PCIE_TX_N => PCIE_TX_N,
189
      PCIE_TX_P => PCIE_TX_P,
190
      bus_clk => bus_clk,
191
      quiesce => quiesce
192
      );
193
194
--  A simple inferred RAM
195
196
  ram_addr <= conv_integer(user_mem_8_addr);
197
  
198
  process (bus_clk)
199
  begin
200
    if (bus_clk'event and bus_clk = '1') then
201
      if (user_w_mem_8_wren = '1') then 
202
        demoarray(ram_addr) <= user_w_mem_8_data;
203
      end if;
204
      if (user_r_mem_8_rden = '1') then
205
        user_r_mem_8_data <= demoarray(ram_addr);
206
      end if;
207
    end if;
208
  end process;
209
210
  user_r_mem_8_empty <= '0';
211
  user_r_mem_8_eof <= '0';
212
  user_w_mem_8_full <= '0';
213
214
--  32-bit loopback
215
216
  fifo_32 : fifo_32x512
217
    port map(
218
      clk        => bus_clk,
219
      srst       => reset_32,
220
      din        => user_w_write_32_data,
221
      wr_en      => user_w_write_32_wren,
222
      rd_en      => user_r_read_32_rden,
223
      dout       => user_r_read_32_data,
224
      full       => user_w_write_32_full,
225
      empty      => user_r_read_32_empty
226
      );
227
228
  reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
229
230
  user_r_read_32_eof <= '0';
231
  
232
--  8-bit loopback
233
234
  fifo_8 : fifo_8x2048
235
    port map(
236
      clk        => bus_clk,
237
      srst       => reset_8,
238
      din        => user_w_write_8_data,
239
      wr_en      => user_w_write_8_wren,
240
      rd_en      => user_r_read_8_rden,
241
      dout       => user_r_read_8_data,
242
      full       => user_w_write_8_full,
243
      empty      => user_r_read_8_empty
244
      );
245
246
    reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
247
248
    user_r_read_8_eof <= '0';
249
  
250
end sample_arch;

Why if I try to push user_w_write_8_data to user_r_read_8_data I get 
error but if I try to push a stitic value to user_r_read_8_data it 
works?

This works:
1
process (bus_clk)
2
  begin
3
    if (bus_clk'event and bus_clk = '1') then
4
      if (user_w_mem_8_wren = '1') then 
5
        user_r_read_8_data <= "00000001";
6
      end if;
7
    end if;
8
  end process;


This works too:
1
process (bus_clk)
2
  begin
3
    if (bus_clk'event and bus_clk = '1') then
4
      if (user_w_mem_8_wren = '1') then 
5
        tmp <= user_w_write_8_data;
6
      end if;
7
    end if;
8
  end process;


But this does not work:
1
process (bus_clk)
2
  begin
3
    if (bus_clk'event and bus_clk = '1') then
4
      if (user_w_mem_8_wren = '1') then 
5
        user_r_read_8_data <= user_w_write_8_data;
6
      end if;
7
    end if;
8
  end process;

This is the error I get:
1
ImplementationOpt Design[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[0].
2
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[1].
3
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[2].
4
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[3].
5
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[4].
6
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[5].
7
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[6].
8
[Opt 31-37] Multi-driver net found in the design: fifo_8/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/dout[7].

Can somebody explain me why the last code does not work?

von Lothar M. (lkmiller) (Moderator)


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What do you do with tmp in the second case? Nothing? Then it is simply 
optimized away...

Obviously the signal in question is connected to an output port. And you 
additionally drive a value on it. That's the multisource.

What toolchain and what target do you use?

von Junior H. (Company: University) (junior_hpc)


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Hello. I use Vivado suite 2015 on Xilinx Artix 7. Well, in both second 
and third case, I copy the value of user_w_write_8_data in an other 
variable/signal. Can you please give me more details about this issue? 
By signal in question, do you mean user_r_read_8_data? Thanks.

von Junior H. (Company: University) (junior_hpc)


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Lothar M. wrote:

> Obviously the signal in question is connected to an output port. And you
> additionally drive a value on it. That's the multisource.

Actually, what I want to do is to take the value of user_w_write_8_data 
and put it in user_r_read_8_data. Is there any solution for this 
problem?

von Achim S. (Guest)


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Junior H. wrote:
> Actually, what I want to do is to take the value of user_w_write_8_data
> and put it in user_r_read_8_data. Is there any solution for this
> problem?

You should configure your fifo_8 as "fist word fall through fifo" (maybe 
in your toolchain the parameter of the fifo-generator is called slightly 
different). Then - in case the fifo is empty prior to the write access - 
the write data appears at the fifo output immediately after writing it.

If the fifo is not empty prior to the write access, then of course the 
"old" data remains at the fifo output (until you activate the read 
enable input for the required number of cycles). That's just ordinary 
fifo-functionality. If you want a different behaviour, you should not 
use a fifo ;-)

von Chris (Guest)


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If you want to read on the PC from your FPGA, you have to reconnect the 
loopback FIFO. In this FIFO you put in the data from the PC, and if the 
PC wants to read from the FPGA, it reads what in the FIFO is.
So, the xillydemo example does exactly what you want. If you want to put 
some other data into the FIFO, you have to disconnect the 
user_w_write_8_data (and enable signal) from the FIFO, and connect 
whatever you want to transmit with it.

von Junior H. (Company: University) (junior_hpc)


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Chris wrote:
> If you want to read on the PC from your FPGA, you have to
> reconnect the
> loopback FIFO. In this FIFO you put in the data from the PC, and if the
> PC wants to read from the FPGA, it reads what in the FIFO is.
> So, the xillydemo example does exactly what you want. If you want to put
> some other data into the FIFO, you have to disconnect the
> user_w_write_8_data (and enable signal) from the FIFO, and connect
> whatever you want to transmit with it.

Achim S. wrote:
> Junior H. wrote:
>> Actually, what I want to do is to take the value of user_w_write_8_data
>> and put it in user_r_read_8_data. Is there any solution for this
>> problem?
>
> You should configure your fifo_8 as "fist word fall through fifo" (maybe
> in your toolchain the parameter of the fifo-generator is called slightly
> different). Then - in case the fifo is empty prior to the write access -
> the write data appears at the fifo output immediately after writing it.
>
> If the fifo is not empty prior to the write access, then of course the
> "old" data remains at the fifo output (until you activate the read
> enable input for the required number of cycles). That's just ordinary
> fifo-functionality. If you want a different behaviour, you should not
> use a fifo ;-)

Thank you for the answers. BTW, I am newbie. I understood the idea but I 
don't have idea how to implement it. Could you give me an hint? Code 
examples would be perfect. Thanks

von Junior H. (Company: University) (junior_hpc)


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Chris wrote:
> If you want to read on the PC from your FPGA, you have to reconnect the
> loopback FIFO. In this FIFO you put in the data from the PC, and if the
> PC wants to read from the FPGA, it reads what in the FIFO is.
> So, the xillydemo example does exactly what you want. If you want to put
> some other data into the FIFO, you have to disconnect the
> user_w_write_8_data (and enable signal) from the FIFO, and connect
> whatever you want to transmit with it.

My idea is to put some other data on tmp signal and then put tmp into 
the FIFO. As you suggested me, I disconnected the user_w_write_8_data 
and put tmp instead of user_w_write_8_data. Now, my FIFO is like this:
1
fifo_8 : fifo_8x2048
2
    port map(
3
      clk        => bus_clk,
4
      srst       => reset_8,
5
      din        => tmp,
6
      wr_en      => user_w_write_8_wren,
7
      rd_en      => user_r_read_8_rden,
8
      dout       => user_r_read_8_data,
9
      full       => user_w_write_8_full,
10
      empty      => user_r_read_8_empty
11
      );

Few questions. What do you mean by
> (and enable signal) ?
Do you mean tmp signal?

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