Hello, this is my first post. I'm very new to digital logic and VHDL. I started by making some VHDL for just a clock, which I was able to compile with VHDL just fine, and simulate, and view the output in gtkwave. What I was hoping to do next is just an 8-bit ripple adder. However, I'm stuck on an error. The following VHDL: library ieee; use ieee.std_logic_1164.all; entity and_gate is port ( a, b: in std_logic; a_and_b: out std_logic ); end; architecture behavior of and_gate is begin process (a, b) begin a_and_b <= a and b; end process; end; entity xor_gate is port ( a: in std_logic; b: in std_logic; a_xor_b: out std_logic ); end; Fails with the errors: $ ghdl -a 8_bit_adder.vhdl 8_bit_adder.vhdl:23:15: no declaration for "std_logic" 8_bit_adder.vhdl:24:15: no declaration for "std_logic" 8_bit_adder.vhdl:25:22: no declaration for "std_logic" ghdl: compilation error The error goes away if I delete the "xor_gate" entity. I'm surprised at the error as I don't know why I wouldn't be able to use the same type (std_logic) several times. Please help! :)

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Locked by Moderator

Edmund wrote: > library ieee; > use ieee.std_logic_1164.all; Thats missing before the second entity. Each VHDL module starts with the used libraries...

Unfortunately, I've run into another error that I don't know how to interpret. The following VHDL:

1 | library ieee; |

2 | use ieee.std_logic_1164.all; |

3 | |

4 | entity and_gate is |

5 | port ( |

6 | a: in std_logic; |

7 | b: in std_logic; |

8 | a_and_b: out std_logic |

9 | ```
);
``` |

10 | end; |

11 | |

12 | architecture behavior of and_gate is |

13 | ```
begin
``` |

14 | process (a, b) |

15 | ```
begin
``` |

16 | a_and_b <= a and b; |

17 | end process; |

18 | end; |

19 | |

20 | library ieee; |

21 | use ieee.std_logic_1164.all; |

22 | |

23 | entity xor_gate is |

24 | port ( |

25 | a: in std_logic; |

26 | b: in std_logic; |

27 | a_xor_b: out std_logic |

28 | ```
);
``` |

29 | end; |

30 | |

31 | architecture behavior of xor_gate is |

32 | ```
begin
``` |

33 | process (a, b) |

34 | ```
begin
``` |

35 | a_xor_b <= a xor b; |

36 | end process; |

37 | end; |

38 | |

39 | library ieee; |

40 | use ieee.std_logic_1164.all; |

41 | |

42 | entity half_adder is |

43 | port ( |

44 | a: in std_logic; |

45 | b: in std_logic; |

46 | sum: out std_logic; |

47 | carry: out std_logic |

48 | ```
);
``` |

49 | end; |

50 | |

51 | architecture structure of half_addr is |

52 | component and_gate is |

53 | port ( |

54 | a: in std_logic; |

55 | b: in std_logic; |

56 | a_and_b: out std_logic |

57 | ```
);
``` |

58 | end component; |

59 | |

60 | component xor_gate is |

61 | port ( |

62 | a: in std_logic; |

63 | b: in std_logic; |

64 | a_xor_b: out std_logic |

65 | ```
);
``` |

66 | end component; |

67 | ```
begin
``` |

68 | g1: xor_gate port map ( |

69 | a => a, |

70 | b => b, |

71 | a_xor_b => sum |

72 | ```
);
``` |

73 | g2: and_gate port map ( |

74 | a => a, |

75 | b => b, |

76 | a_and_b => carry |

77 | ```
);
``` |

78 | end; |

Yields: $ ghdl -a 8_bit_adder.vhdl 8_bit_adder.vhdl:53:14: entity 'half_addr' was not analysed ghdl: compilation error It is probably obvious that this is my first structural VHDL architecture, I'm having trouble finding a good resource on VHDL syntax/semantics. Thank you in advance.

:
Edited by Moderator

Oh uh.. nevermind. "half_addr" versus "half_adder".

Edmund wrote: > Oh uh.. nevermind Ok, but in the next post with VHDL code try that (its to be found a few lines above the edit box):

1 | Formatting options |

2 | [vhdl]VHDL code[/vhdl] |

:
Edited by Moderator

Hi, I was trying to combine my 4:1 mux and register together. By using the method above, where in the code should i put my processes of both the components? in the port map?

Danial Sadiq wrote: > By using the method above There you can see two entities and_gate and xor_gate which are used as components in a top level entity half_adder. > in the port map? In aport mapyou have to put theportsof the entity. And that entity afterwards is instantiated as a component in a top level entity. You can see, that the two processes in the two entities and_gate and xor_gate do not show up in any port map. > I was trying to combine my 4:1 mux and register together. Which mux and which registers? I can't see no code with that... Post your code (wrap it as described with the [vhdl] tags), then we can discuss your particular problem.

Please use in one VHDL-file only one entry. Your code will be better readable. Half-add and full-add are only simple demonstrators. The VHDL-language has for this the operator + for signed and unsigned signal.