1 | `timescale 1ns / 1ps
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2 | //////////////////////////////////////////////////////////////////////////////////
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3 | // Company:
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4 | // Engineer:
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5 | //
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6 | // Create Date: 14:20:50 04/10/2015
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7 | // Design Name:
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8 | // Module Name: DashClock
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9 | // Project Name:
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10 | // Target Devices:
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11 | // Tool versions:
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12 | // Description:
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13 | //
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14 | // Dependencies:
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15 | //
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16 | // Revision:
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17 | // Revision 0.01 - File Created
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18 | // Additional Comments:
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19 | //
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20 | //////////////////////////////////////////////////////////////////////////////////
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21 | module DashClock(
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22 | input START, STOP, CSS, RESET, clk,
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23 | output a,b,c,d,e,f,g
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24 | );
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25 | reg [3:0] Enable;
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26 | reg [15:0]TM;
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27 | reg [18:0] Count ;
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28 | wire Count_Max;
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29 |
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30 | always @(posedge clk) //clk pulse at every 20ns
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31 | begin
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32 |
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33 | if(Count == 500000)
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34 | Count <= 0;
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35 | else if (Count <= 500000)
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36 | Count <= Count + 1;
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37 | end
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38 |
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39 | assign Count_Max = ((Count == 500000)?1'b1:1'b0);
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40 |
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41 |
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42 |
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43 | reg Stop_Flg = 0;
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44 |
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45 | always @(posedge clk or posedge RESET)
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46 | begin
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47 | if(RESET)
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48 | begin
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49 | TM [3:0] <= 0;
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50 | TM [3:0] <= 0;
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51 | TM [3:0] <= 0;
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52 | TM [3:0] <= 0;
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53 | end
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54 |
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55 | if (START == 1)
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56 | begin
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57 | TM <= 0;
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58 |
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59 |
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60 | while (STOP !== Stop_Flg)
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61 | begin
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62 |
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63 | if(Count_Max)
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64 | begin
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65 |
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66 | if(TM [3:0] == 4'b1001)
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67 | begin
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68 |
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69 | TM [3:0] <= 4'b0000;
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70 | if(TM [7:4] == 9)
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71 | begin
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72 | TM [7:4] <= 4'b0000;
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73 |
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74 | if(TM [11:8] == 9)
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75 | begin
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76 | TM [11:8] <= 4'b0000;
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77 |
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78 | if(TM [15:12] == 9)
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79 | begin
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80 | Stop_Flg <= 1;
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81 | else // line 85 error
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82 | TM [15:12] <= TM [15:12] +1;
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83 | end
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84 |
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85 | else
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86 | TM [11:8] <= TM [11:8] +1;
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87 | end
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88 |
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89 | else
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90 | TM [7:4] <= TM [7:4] +1;
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91 | end
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92 |
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93 | else
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94 | TM [3:0] <= TM [3:0] + 1;
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95 | end// TM [3:0]
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96 |
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97 | end // If statement Count Max
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98 | end // while
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99 | end // IF Statement Start =1?
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100 | end // always @ Clock
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101 |
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102 | reg [17:0] Mux_Count;
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103 | reg [6:0] Sev_Seg;
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104 | reg DP;
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105 |
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106 | always @ (posedge clk)
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107 | begin
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108 | Mux_Count <= Mux_Count +1;
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109 | end
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110 |
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111 | always @ (*)
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112 | begin
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113 | case(Mux_Count[17:16])
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114 |
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115 | 2'b00 :
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116 | begin
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117 | Sev_Seg <= TM[3:0];
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118 | Enable <= 4'b0001;
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119 | DP <= 0;
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120 | end
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121 |
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122 | 2'b01 :
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123 | begin
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124 | Sev_Seg <= TM[7:4];
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125 | Enable <= 4'b0010;
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126 | DP <= 1;
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127 | end
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128 |
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129 | 2'b10 :
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130 | begin
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131 | Sev_Seg <= TM[11:8];
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132 | Enable = 4'b0100;
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133 | DP <= 0;
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134 | end
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135 |
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136 | 2'b11 :
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137 | begin
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138 | Sev_Seg <= TM[15:12];
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139 | Enable <= 4'b1000;
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140 | DP <= 0;
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141 | end
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142 | endcase
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143 | end
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144 |
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145 | reg [6:0] Convert;
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146 | always @ (*)
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147 | begin
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148 | case(Sev_Seg)
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149 | 4'b0000 : Convert <= 7'b1111110;
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150 | 4'b0001 : Convert <= 7'b0110000;
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151 | 4'b0010 : Convert <= 7'b1101101;
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152 | 4'b0011 : Convert <= 7'b1111001;
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153 | 4'b0100 : Convert <= 7'b0110011;
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154 | 4'b0101 : Convert <= 7'b1011011;
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155 | 4'b0110 : Convert <= 7'b1011111;
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156 | 4'b0111 : Convert <= 7'b1110000;
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157 | 4'b1000 : Convert <= 7'b1111111;
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158 | 4'b1001 : Convert <= 7'b1111011;
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159 | endcase
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160 | end
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161 | assign {a,b,c,d,e,f,g} = Convert;
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162 |
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163 |
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164 | endmodule
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