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Forum: FPGA, VHDL & Verilog Help Beginner Make Stop watch


Help Beginner Make Stop watch
von John (Guest)

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Trying to make a stop watch that will stop when you hit the stop button 
that is what the while loop is for. I am an amateur and would really 
appreciate any help.

Thank You!

ERROR:HDLCompiler:806 - "/home/melvin/Desktop/Modern 
DIG/DashClock/DashClock.v" Line 85: Syntax error near "else".


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`timescale 1ns / 1ps

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//////////////////////////////////////////////////////////////////////////////////

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// Company: 

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// Engineer: 

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// 

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// Create Date:    14:20:50 04/10/2015 

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// Design Name: 

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// Module Name:    DashClock 

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// Project Name: 

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// Target Devices: 

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// Tool versions: 

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// Description: 

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//

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// Dependencies: 

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//

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// Revision: 

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// Revision 0.01 - File Created

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// Additional Comments: 

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//

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//////////////////////////////////////////////////////////////////////////////////

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module DashClock(

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  input  START, STOP, CSS, RESET, clk,

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  output a,b,c,d,e,f,g

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    );

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   reg [3:0] Enable;

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   reg [15:0]TM;

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   reg [18:0] Count ;

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   wire Count_Max;

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  always @(posedge clk)  //clk pulse at every 20ns

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   begin

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    if(Count == 500000)

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       Count <= 0;

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    else if (Count <= 500000)

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       Count <= Count + 1;

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   end

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      assign Count_Max = ((Count == 500000)?1'b1:1'b0);

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    reg Stop_Flg = 0;

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    always @(posedge clk or posedge RESET)

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    begin

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    if(RESET)

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      begin 

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      TM [3:0] <= 0;

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      TM [3:0] <= 0;

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      TM [3:0] <= 0;

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      TM [3:0] <= 0;

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      end

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    if (START == 1)  

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      begin

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      TM <= 0;

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while (STOP !== Stop_Flg)

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   begin

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     if(Count_Max)

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  begin  

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   if(TM [3:0] == 4'b1001)

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      begin

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        TM [3:0] <= 4'b0000;

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    if(TM [7:4] == 9)

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                     begin

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          TM [7:4] <= 4'b0000;

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      if(TM [11:8] == 9)

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          begin

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            TM [11:8] <= 4'b0000;

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        if(TM [15:12] == 9)

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            begin

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                Stop_Flg <= 1;

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        else  // line 85 error                                                                                                                       

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           TM [15:12] <= TM [15:12] +1;

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                                end

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         else 

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                       TM [11:8] <= TM [11:8] +1;

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               end

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             else

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        TM [7:4] <= TM [7:4] +1;

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      end

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    else

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      TM [3:0] <= TM [3:0] + 1;

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    end// TM [3:0]

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             end // If statement Count Max

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         end // while

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       end // IF Statement Start =1?

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     end // always @ Clock

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   reg [17:0] Mux_Count;

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  reg [6:0]  Sev_Seg;

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  reg        DP;

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  always @ (posedge clk)

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    begin

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      Mux_Count <= Mux_Count +1;

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    end

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  always @ (*)

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    begin

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      case(Mux_Count[17:16])

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       2'b00 :

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        begin

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        Sev_Seg <= TM[3:0];

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        Enable <= 4'b0001;

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        DP <= 0;

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        end

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       2'b01 :

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        begin

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        Sev_Seg <= TM[7:4];

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        Enable <= 4'b0010;

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        DP <= 1;

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        end

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       2'b10 :

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        begin

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        Sev_Seg <= TM[11:8];

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        Enable = 4'b0100;

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        DP <= 0;

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        end

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       2'b11 :

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        begin

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        Sev_Seg <= TM[15:12];

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        Enable <= 4'b1000;

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        DP <= 0;

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        end

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      endcase

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     end

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    reg [6:0] Convert;

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    always @ (*)

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      begin

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       case(Sev_Seg)

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        4'b0000 : Convert <= 7'b1111110;

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        4'b0001 : Convert <= 7'b0110000;

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        4'b0010 : Convert <= 7'b1101101;

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        4'b0011 : Convert <= 7'b1111001;

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        4'b0100 : Convert <= 7'b0110011;

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        4'b0101 : Convert <= 7'b1011011;

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        4'b0110 : Convert <= 7'b1011111;

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        4'b0111 : Convert <= 7'b1110000;

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        4'b1000 : Convert <= 7'b1111111;

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        4'b1001 : Convert <= 7'b1111011;

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        endcase

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      end

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    assign {a,b,c,d,e,f,g} = Convert;

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endmodule


  


  




  

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    Re: Help Beginner Make Stop watch
  


  

    

      von
      
        Lattice User (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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John wrote:
>
> ERROR:HDLCompiler:806 - "/home/melvin/Desktop/Modern
> DIG/DashClock/DashClock.v" Line 85: Syntax error near "else".
>

This is caused by a nesting error. 2 lines before is an unclosed 
"begin".
Hard to spot, because of very bad indentation.

But there is a big rookie error, many beginners with programming (C, 
etc) background make: The while does not do what you expect!

Beginners should use while/for/... loops only in TEST benches, but never 
in anything which is targeted to hardware (i.e. FPGA).
Create a finite state machine instead.

(Your LED muxer is an example of a simple FSM)

  


  




  

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    Re: Help Beginner Make Stop watch
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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John wrote:
> Trying to make a stop watch
Try this original code there:
http://simplefpga.blogspot.de/2012/07/to-code-stopwatch-in-verilog.html

BTW: there's a design flaw in it making the clock inaccurate for 
1/5000000. "That's not that much!" you may say, but in fact its a very 
basic problem in a beginners design. The prescaler counts 5000001 steps 
instead only 5000000, one step too much... :-o

  


  



  

  
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    Re: Help Beginner Make Stop watch
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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One more thing is this here:

if(RESET)
begin
  TM [3:0] <= 0;
  TM [3:0] <= 0;
  TM [3:0] <= 0;
  TM [3:0] <= 0;
end

Nice, isn't it? :-o

  


  



  

  
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