`timescale 1ns / 1ps
module main(
input clk,
output Hsync,
output Vsync,
output reg [3:0] vgaGreen,
output reg [3:0] vgaBlue,
output reg [3:0] vgaRed,
input Modechanger
);
//Declare some counters
reg [23:0] clkCounter;
reg [10:0] Hcounter;
reg [10:0] Vcounter;
localparam threshold = 2000000; //25MHz
//Clock divider
always @ (posedge (clk)) begin
if (clkCounter == threshold -1)
clkCounter <= 24'b0;
else
clkCounter <= clkCounter + 1;
end
//Check and set position
always @ (posedge (clk)) begin
if (Hcounter < 799)
Hcounter <= Hcounter + 1;
else begin
Hcounter <= 0;
if (Vcounter < 524) begin
Vcounter <= Vcounter + 1;
end
else begin
Vcounter <= 0;
end
end
end
//Draw when in this range
assign Hsync = (Hcounter < 96) ? 0:1;
assign Vsync = (Vcounter < 2) ? 0:1;
//How to draw, and what to draw
always @ (Hcounter or Vcounter)begin
//if inside drawable zone
if (Vcounter >34 && Vcounter < 516)
begin
if (Hcounter > 143 && Hcounter < 785)
begin
//Mode 1: Draw a red cross hair line, and green
background
if(ModeChanger) begin
if (Hcounter == 464 || Vcounter == 275)
begin
vgaGreen = 4'b0000;
vgaRed = 4'b1111;
vgaBlue = 4'b0000;
end
else begin
vgaGreen = 4'b1111;
vgaRed = 4'b0000;
vgaBlue = 4'b0000;
end
end
//Mode 2: green screen
else
vgaGreen = 4'b1111;
vgaRed = 4'b0000;
vgaBlue = 4'b0000;
end
end
else begin
vgaGreen = 4'b0000;
vgaRed = 4'b0000;
vgaBlue = 4'b0000;
end
end
endmodule
I'm trying to draw something to my screen using my FPGA board, this is
the code I come up with, I'm new to Verilog and I don't really know why
I get the error message "Synth 8-1031 ModeChanger is not declared".
ModeChanger is a switch on my FPGA board.<br>
My first question is what cause the error?<br>
And my second question is will my code work as I expect? (ModeChanger
on, draw a cross hair line, otherwise a green screen)<br>The reason I
ask this question is because I don't have a VGA cable to test it
out.<br>Please help me, thank you so much
TJ wrote: > My first question is what cause the error? Mine is: what part of what toolchain reports that error? TJ wrote: > And my second question is will my code work as I expect? Mine is: what does the simulator say? How does your testbench look like?
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