Im using verilog for a school assignment, and as a computer science 
major, I probably wont be using it again for any more classes, since 
this is the only electrical engineering class I need to take, so I find 
that doing everything at the gate level makes sense. i've seen more 
abstract methods to accomplish what I'm trying to do, but I'd like to 
keep my coding style consistent throughout the project.

What im doing in this module is making a 9-bit 8-to-1 multiplexer by 
putting 9 1-bit 8-to-1 multiplexers in parallel. I've tested my 1-bit 
multiplexer, and it works as intended. my issue is with the 9bit, where 
im moving bits from the input into the nested multiplexers. here is a 
snippit of code

module mux_9b_81(
    input [8:0] r0, r1, r2, r3, r4, r5, r6, r7,
   input [2:0] s,
   output [8:0] q);

   mux81 b0(
    .s(s),
    .d[0](r0[0]),   <-error
    .d[1](r1[0]),
    .d[2](r2[0]),
    .d[3](r3[0]),
    .d[4](r4[0]),
    .d[5](r5[0]),
    .d[6](r6[0]),
    .d[7](r7[0]),
    .q(q[0])
     );
     mux81 bn(
     ...
end module

to explain - mux0 selects the first bit from the selected(s) input, r0
             mux1 selects the second bit from the selected(s) input, r1
             ...
all these bits are combined into q and returned.
I noted where xilinx shows that my error is,
and this error occurs in the same place in each mux81.

is this just a syntax error?
thanks,

-chris