There is some wrong in this code, could y help me to fix it, I want to use it immediately.
1 | library IEEE; |
2 | use IEEE.std_logic_1164.all; |
3 | use IEEE.std_logic_unsigned.all; |
4 | entity vgacore is |
5 | port
|
6 | (
|
7 | rgb: out std_logic_vector(5 downto 0); -- red,green,blue colors |
8 | addr: out std_logic_vector(14 downto 0); -- address into video RAM |
9 | data: in std_logic_vector(7 downto 0); -- data from video RAM |
10 | csb: out std_logic; -- video RAM chip enable |
11 | oeb: out std_logic; -- video RAM output enable |
12 | web: out std_logic -- video RAM write enable |
13 | );
|
14 | end vgacore; |
15 | |
16 | architecture vgacore_arch of vgacore is |
17 | signal vsyncb: std_logic:= '0'; |
18 | signal hsyncb:std_logic:= '0'; |
19 | signal clock: std_logic:= '0'; |
20 | signal reset:std_logic:= '0'; |
21 | signal hcnt: std_logic_vector(8 downto 0); -- horizontal pixel counter |
22 | signal vcnt: std_logic_vector(9 downto 0); -- vertical line counter |
23 | signal pixrg: std_logic_vector(7 downto 0); -- byte-wide register for 4 pixels |
24 | signal blank: std_logic; -- video blanking signal |
25 | signal pblank: std_logic; -- pipelined video blanking signal |
26 | begin
|
27 | |
28 | A: process(clock,reset) |
29 | begin
|
30 | -- reset asynchronously clears pixel counter
|
31 | if reset='1' then |
32 | hcnt <= "000000000"; |
33 | -- horiz. pixel counter increments on rising edge of dot clock
|
34 | elsif (clock'event and clock='1') then |
35 | -- horiz. pixel counter rolls-over after 381 pixels
|
36 | if hcnt<380 then |
37 | hcnt <= hcnt + 1; |
38 | else
|
39 | hcnt <= "000000000"; |
40 | end if; |
41 | end if; |
42 | end process; |
43 | |
44 | B: process(hsyncb,reset) |
45 | begin
|
46 | -- reset asynchronously clears line counter
|
47 | if reset='1' then |
48 | vcnt <= "0000000000"; |
49 | -- vert. line counter increments after every horiz. line
|
50 | elsif (hsyncb'event and hsyncb='1') then |
51 | -- vert. line counter rolls-over after 528 lines
|
52 | if vcnt<527 then |
53 | vcnt <= vcnt + 1; |
54 | else
|
55 | vcnt <= "0000000000"; |
56 | end if; |
57 | end if; |
58 | end process; |
59 | |
60 | C: process(clock,reset) |
61 | begin
|
62 | -- reset asynchronously sets horizontal sync to inactive
|
63 | if reset='1' then |
64 | hsyncb <= '1'; |
65 | -- horizontal sync is recomputed on the rising edge of every dot clock
|
66 | elsif (clock'event and clock='1') then |
67 | -- horiz. sync is low in this interval to signal start of a new line
|
68 | if (hcnt>=291 and hcnt<337) then |
69 | hsyncb <= '0'; |
70 | else
|
71 | hsyncb <= '1'; |
72 | end if; |
73 | end if; |
74 | end process; |
75 | |
76 | D: process(hsyncb,reset) |
77 | begin
|
78 | -- reset asynchronously sets vertical sync to inactive
|
79 | if reset='1' then |
80 | vsyncb <= '1'; |
81 | -- vertical sync is recomputed at the end of every line of pixels
|
82 | elsif (hsyncb'event and hsyncb='1') then |
83 | -- vert. sync is low in this interval to signal start of a new frame
|
84 | if (vcnt>=490 and vcnt<492) then |
85 | vsyncb <= '0'; |
86 | else
|
87 | vsyncb <= '1'; |
88 | end if; |
89 | end if; |
90 | end process; |
91 | |
92 | -- blank video outside of visible region: (0,0) -> (255,479)
|
93 | E: blank <= '1' when (hcnt>=256 or vcnt>=480) else '0'; |
94 | -- store the blanking signal for use in the next pipeline stage
|
95 | F: process(clock,reset) |
96 | begin
|
97 | if reset='1' then |
98 | pblank <= '0'; |
99 | elsif (clock'event and clock='1') then |
100 | pblank <= blank; |
101 | end if; |
102 | end process; |
103 | |
104 | -- video RAM control signals
|
105 | G: |
106 | csb <= '0'; -- enable the RAM |
107 | web <= '1'; -- disable writing to the RAM |
108 | oeb <= blank; -- enable the RAM outputs when video is not blanked |
109 | |
110 | -- The video RAM address is built from the lower 9 bits of the vertical
|
111 | -- line counter and bits 7-2 of the horizontal pixel counter.
|
112 | -- Each byte of the RAM contains four 2-bit pixels. As an example,
|
113 | -- the byte at address ^h1234=^b0001,0010,0011,0100 contains the pixels
|
114 | -- at (row,col) of (^h048,^hD0),(^h048,^hD1),(^h048,^hD2),(^h048,^hD3).
|
115 | H: addr <= vcnt(8 downto 0) & hcnt(7 downto 2); |
116 | |
117 | I: process(clock,reset) |
118 | begin
|
119 | -- clear the pixel register on reset
|
120 | if reset='1' then |
121 | pixrg <= "00000000"; |
122 | -- pixel clock controls changes in pixel register
|
123 | elsif (clock'event and clock='1') then |
124 | -- the pixel register is loaded with the contents of the video
|
125 | -- RAM location when the lower two bits of the horiz. counter
|
126 | -- are both zero. The active pixel is in the lower two bits
|
127 | -- of the pixel register. For the next 3 clocks, the pixel
|
128 | -- register is right-shifted by two bits to bring the other
|
129 | -- pixels in the register into the active position.
|
130 | if hcnt(1 downto 0)="00" then |
131 | pixrg <= data; -- load 4 pixels from RAM |
132 | else
|
133 | pixrg <= "00" & pixrg(7 downto 2); -- right-shift pixel register |
134 | end if; |
135 | end if; |
136 | end process; |
137 | |
138 | -- the color mapper translates each 2-bit pixel into a 6-bit
|
139 | -- color value. When the video signal is blanked, the color
|
140 | -- is forced to zero (black).
|
141 | J: process(clock,reset) |
142 | begin
|
143 | -- blank the video on reset
|
144 | if reset='1' then |
145 | rgb <= "000000"; |
146 | -- update the color outputs on every dot clock
|
147 | elsif (clock'event and clock='1') then |
148 | -- map the pixel to a color if the video is not blanked
|
149 | if pblank='0' then |
150 | case pixrg(1 downto 0) is |
151 | when "00" => rgb <= "110000"; -- red |
152 | when "01" => rgb <= "001100"; -- green |
153 | when "10" => rgb <= "000011"; -- blue |
154 | when others => rgb <= "111111"; -- white |
155 | end case; |
156 | -- otherwise, output black if the video is blanked
|
157 | else
|
158 | rgb <= "000000"; -- black |
159 | end if; |
160 | end if; |
161 | end process; |
162 | |
163 | end vgacore_arch; |
there is some thing wrong ,could you help me to fix it
:
Edited by Moderator
Did you read this: Rules — please read before posting Post long source code as attachment, not in the text Or that: Formatting options specially the part with "VHDL code" shashaxu wrote: > there is some thing wrong ,could you help me to fix it Do you take your car to repair and tell the mechanic: "There's something wrong! Fix it!" No, because then when you get the car back there may be noted on the bill: "Fixed something!"... Please write WHAT is wrong. And HOW you did find that out. And WHETHER you have a test bench or not.
My VHDL files never ends with TXT. Why does yours? BTW: I merged your two threads into one.