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von Read a picture into bram (Guest)


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There is some wrong in this code, could y help me to fix it, I want to 
use it immediately.

von shashaxu (Guest)


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1
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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entity vgacore is
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    port
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    (
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        rgb: out std_logic_vector(5 downto 0);    -- red,green,blue colors
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        addr: out std_logic_vector(14 downto 0);    -- address into video RAM
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        data: in std_logic_vector(7 downto 0);    -- data from video RAM
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        csb: out std_logic;        -- video RAM chip enable
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        oeb: out std_logic;        -- video RAM output enable
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        web: out std_logic        -- video RAM write enable
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    );
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end vgacore;
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architecture vgacore_arch of vgacore is
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signal vsyncb:  std_logic:= '0';
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signal hsyncb:std_logic:= '0';
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signal clock:  std_logic:= '0';
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signal reset:std_logic:= '0';
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signal hcnt: std_logic_vector(8 downto 0);    -- horizontal pixel counter
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signal vcnt: std_logic_vector(9 downto 0);    -- vertical line counter
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signal pixrg: std_logic_vector(7 downto 0);    -- byte-wide register for 4 pixels
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signal blank: std_logic;                    -- video blanking signal
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signal pblank: std_logic;                    -- pipelined video blanking signal
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begin
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A: process(clock,reset)
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begin
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    -- reset asynchronously clears pixel counter
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    if reset='1' then
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        hcnt <= "000000000";
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    -- horiz. pixel counter increments on rising edge of dot clock
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    elsif (clock'event and clock='1') then
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        -- horiz. pixel counter rolls-over after 381 pixels
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        if hcnt<380 then
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            hcnt <= hcnt + 1;
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        else
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            hcnt <= "000000000";
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        end if;
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    end if;
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end process;
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B: process(hsyncb,reset)
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begin
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    -- reset asynchronously clears line counter
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    if reset='1' then
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        vcnt <= "0000000000";
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    -- vert. line counter increments after every horiz. line
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    elsif (hsyncb'event and hsyncb='1') then
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        -- vert. line counter rolls-over after 528 lines
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        if vcnt<527 then
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            vcnt <= vcnt + 1;
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        else
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            vcnt <= "0000000000";
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        end if;
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    end if;
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end process;
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C: process(clock,reset)
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begin
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    -- reset asynchronously sets horizontal sync to inactive
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    if reset='1' then
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        hsyncb <= '1';
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    -- horizontal sync is recomputed on the rising edge of every dot clock
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    elsif (clock'event and clock='1') then
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        -- horiz. sync is low in this interval to signal start of a new line
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        if (hcnt>=291 and hcnt<337) then
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            hsyncb <= '0';
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        else
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            hsyncb <= '1';
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        end if;
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    end if;
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end process;
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D: process(hsyncb,reset)
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begin
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    -- reset asynchronously sets vertical sync to inactive
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    if reset='1' then
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        vsyncb <= '1';
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    -- vertical sync is recomputed at the end of every line of pixels
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    elsif (hsyncb'event and hsyncb='1') then
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        -- vert. sync is low in this interval to signal start of a new frame
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        if (vcnt>=490 and vcnt<492) then
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            vsyncb <= '0';
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        else
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            vsyncb <= '1';
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        end if;
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    end if;
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end process;
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-- blank video outside of visible region: (0,0) -> (255,479)
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E: blank <= '1' when (hcnt>=256 or vcnt>=480) else '0';
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-- store the blanking signal for use in the next pipeline stage
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F: process(clock,reset)
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begin
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    if reset='1' then
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        pblank <= '0';
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    elsif (clock'event and clock='1') then
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        pblank <= blank;
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    end if;
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end process;
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-- video RAM control signals
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G:
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csb <= '0';        -- enable the RAM
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web <= '1';        -- disable writing to the RAM
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oeb <= blank;    -- enable the RAM outputs when video is not blanked
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-- The video RAM address is built from the lower 9 bits of the vertical
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-- line counter and bits 7-2 of the horizontal pixel counter.
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-- Each byte of the RAM contains four 2-bit pixels.  As an example,
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-- the byte at address ^h1234=^b0001,0010,0011,0100 contains the pixels
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-- at (row,col) of (^h048,^hD0),(^h048,^hD1),(^h048,^hD2),(^h048,^hD3).
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H: addr <= vcnt(8 downto 0) & hcnt(7 downto 2);
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I: process(clock,reset)
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begin
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    -- clear the pixel register on reset
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    if reset='1' then
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        pixrg <= "00000000";
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    -- pixel clock controls changes in pixel register
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    elsif (clock'event and clock='1') then
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        -- the pixel register is loaded with the contents of the video
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        -- RAM location when the lower two bits of the horiz. counter
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        -- are both zero.  The active pixel is in the lower two bits
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        -- of the pixel register.  For the next 3 clocks, the pixel
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        -- register is right-shifted by two bits to bring the other
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        -- pixels in the register into the active position.
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        if hcnt(1 downto 0)="00" then
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            pixrg <= data;    -- load 4 pixels from RAM
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        else
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            pixrg <= "00" & pixrg(7 downto 2);    -- right-shift pixel register
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        end if;
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    end if;
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end process;
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-- the color mapper translates each 2-bit pixel into a 6-bit
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-- color value.  When the video signal is blanked, the color
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-- is forced to zero (black).
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J: process(clock,reset)
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begin
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    -- blank the video on reset
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    if reset='1' then
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        rgb <= "000000";
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    -- update the color outputs on every dot clock
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    elsif (clock'event and clock='1') then
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        -- map the pixel to a color if the video is not blanked
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        if pblank='0' then
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            case pixrg(1 downto 0) is
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                when "00" =>   rgb <= "110000";    -- red
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                when "01" =>   rgb <= "001100";    -- green
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                when "10" =>   rgb <= "000011";    -- blue
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                when others => rgb <= "111111";    -- white
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            end case;
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        -- otherwise, output black if the video is blanked
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        else
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            rgb <= "000000";    -- black
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        end if;
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    end if;
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end process;
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end vgacore_arch;



there is some thing wrong ,could you help me to fix it

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Did you read this:
Rules — please read before posting
Post long source code as attachment, not in the text

Or that:
Formatting options
specially the part with "VHDL code"

shashaxu wrote:
> there is some thing wrong ,could you help me to fix it
Do you take your car to repair and tell the mechanic: "There's something 
wrong! Fix it!"
No, because then when you get the car back there may be noted on the 
bill: "Fixed something!"...

Please write WHAT is wrong. And HOW you did find that out. And WHETHER 
you have a test bench or not.

von Lothar M. (lkmiller) (Moderator)


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My VHDL files never ends with TXT. Why does yours?

BTW: I merged your two threads into one.

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