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Forum: FPGA, VHDL & Verilog Test bench I2C (vhdl)


von Javier P. (lascameador)


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hi guys!
I've developed two i2c components.
1
u1: SlaveI2CA generic map (SLAVE_ADDR) port map(scl,sda1,clk,rst,starting1,sda2);
2
u2: SlaveI2CB generic map (SLAVE_ADDR) port map(scl,sda3,clk,rst,starting2,sda4);

I want to connect sda2 and sda3 with a pullup resistor (in simulation) 
but i don't know how to do this.
When I write 'Z' or '0' the slave works,while it has already been 
programmed ,but i don't know how to develope this function in 
simulation.

any advices??
thanks ;)

von Lothar M. (lkmiller) (Moderator)


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Javier PA wrote:
> but i don't know how to develope this function in simulation.
Try it with Google translator:
http://www.lothar-miller.de/s9y/archives/91-Schalter-und-Bruecke.html

I would take the switch model and connect it with a pullup (='H') this 
way:
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 SDA_A --- Switch --- 'H' --- Switch --- SDA_B
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 SCL_A --- Switch --- 'H' --- Switch --- SCL_B

Of course the switch model could be simplified to a Zero-Ohm this way:
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity zeroohm is
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    Port ( A : inout  STD_LOGIC;
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           B : inout  STD_LOGIC);
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end swbidi;
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architecture Behavioral of zeroohm is
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begin
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  process
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    variable thentime : time;
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  begin
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    wait on A, B until thentime /= now;
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    -- Break
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    thentime := now;
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    A <= 'Z';
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    B <= 'Z';
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    wait for 0 ns;
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    -- Make
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    A <= B;
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    B <= A;
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  end process;
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end Behavioral;

: Edited by Moderator

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