Forum: FPGA, VHDL & Verilog VHDL project errors

von Saeid S. (saeiddieas)

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Hi every body,
I have 3 errors in my VHDL project,
is there any body to help me?
Project is for RF PROTOCOL.

von Lothar M. (lkmiller) (Moderator)

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Saeid Syd wrote:
> I have 3 errors in my VHDL project
And now we should find this bugs on our own?
What about telling us what the toolchain (btw: which one?) tells 

It sounds like you give your car to a mechanic and tell him:
I have 3 problems with my car!

I already found a major design flaw:
use ieee.numeric_std.all;
This may not cause problems up to now, but with all those libs together 
you have some double definitions of data types.

My suggestion ist:
Do NOT ust the od std_logic_xxxx libs. Instead use solely the 
numeric_std. It has all you will need. Your teacher should tell you 

And also this here is NOT a neat idea:
      id_V2 : inout std_logic_vector (15 downto 0); 
      trame_moins_CS : inout natural
Use INOUT solely for real bidirectional ports. Do NOT use it for 
lazyness to read back a OUT port in you design.

And also this here is not nice:
      trame_moins_CS : inout natural
  signal adresse : integer;

  --signal trame_moins_CS : natural;
  signal taille_data : natural ;
  signal taille_trame : integer ;
You should not use an integer without a RANGE. Otherwise the simulator 
cannot find a overflow...

von Saeid S. (saeiddieas)

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Thanks a lot, you made my day, i'm going to check it.


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