Saeid Syd wrote:
> I have 3 errors in my VHDL project
And now we should find this bugs on our own?
What about telling us what the toolchain (btw: which one?) tells
you?
It sounds like you give your car to a mechanic and tell him:
I have 3 problems with my car!
I already found a major design flaw:
1 | use ieee.numeric_std.all;
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2 | USE IEEE.STD_LOGIC_ARITH.all;
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3 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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This may not cause problems up to now, but with all those libs together
you have some double definitions of data types.
My suggestion ist:
Do NOT ust the od std_logic_xxxx libs. Instead use solely the
numeric_std. It has all you will need. Your teacher should tell you
this...
And also this here is NOT a neat idea:
1 | id_V2 : inout std_logic_vector (15 downto 0);
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2 | ...
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3 | trame_moins_CS : inout natural
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Use INOUT solely for real bidirectional ports. Do NOT use it for
lazyness to read back a OUT port in you design.
And also this here is not nice:
1 | trame_moins_CS : inout natural
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2 | :
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3 | :
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4 | signal adresse : integer;
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5 | |
6 | --signal trame_moins_CS : natural;
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7 | signal taille_data : natural ;
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8 | signal taille_trame : integer ;
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You should not use an integer without a RANGE. Otherwise the simulator
cannot find a overflow...