you can start with pseudo code and analyze the logic at first.

perhaps you see it, otherwise make a truth table and you receive:

g_out = x and not(y)
e_out = x and y

you also need a bigger truth table to take g_in and e_in in 
consideration:

for example:
g_out = (x and not(y)) or g_in

the rest is verilog Basic knowledge

Thank you Klakx

But I'm pretty new to Verilog and this is my 2nd project. I don't have 
enough knowledge yet :).

I'd be thankful if anyone could help me more explaining the requirements 
and any codes that helps me starting this.
 Regards

John just make a first try with testbench, your component and the 
pseudo-code and then we can help you.

you must be in my ECE171 class... this project SUUUCKS!

OK... this material is fun and gratifying... procrastinating and 
stressing is what sucks... can I post here here for advice on this same 
project?

Thank you... I have a module built for my one bit comparator... kinda 
stumped on the test bench tho. here's what I have so far:

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module oneBitComparator (X, Y, Ein, Gin, Eout, Gout);

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input X, Y, Ein, Gin;

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output Eout, Gout;

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assign Eout = (X & Y) | (~X & ~Y);

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assign Gout = (X & ~Y);

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endmodule

I really wasn't sure what do do with those inputs on the 1-bit 
comparator... how would here be "equal or greater" (Gin, Ein) inputs 
when there is no previous instance of the module?

I'm sorry but i'm very new to this, and I'm getting a little frantic

Ok... was i mistaken in my assumption that x and y would be my control 
bits?

also i was slightly confused by your ruth table showing ein true for all 
x and y

i'm sorry, i meant to say select bits

Lothar Miller wrote:

>> how would here be "equal or greater" (Gin, Ein) inputs when there is no
>> previous instance of the module?
> Then the "previous" result is neither greater nor is it equal. So both
> of them will be '0'.

It should be set to equal, otherwise the end result can't be equal at 
all.

I realized that almost simultaneously as you posted it; Thank you SO 
much for the confirmation!!

I'm thinking I need to redraw my truth table to account for all possible 
combinations of ein and gin, then rewrite my boolean expressions

here's the truth table i came up with:

Am i correct in assuming that when gin is true gout will be true as 
well?

the Boolean equation I came up with is

Gout= ~Ein * Gin + Ein * ~Gin  x  ~y

Eout= Ein * ~Gin * ~x * ~y + Ein * ~Gin  x  y

sorry i kinda botched that... this is correct

Gout= ~Ein * Gin + Ein * ~Gin  x *  ~y

Eout= Ein * ~Gin * ~x * ~y + Ein * ~Gin *x*y

you seem to be missing 1001 on your truth table

well my truth table and Gout equation was wrong, but i think i fixed it.

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module oneBitComparator (X, Y, Ein, Gin, Eout, Gout);

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input X, Y, Ein, Gin;

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output Eout, Gout;

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 assign Eout = (Ein & ~Gin & X & Y) | (Ein & ~Gin & ~X & ~Y);

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 assign Gout = (~Ein & Gin & X) | (Ein & ~Gin & ~Y) | (Ein & ~Gin & X & ~y);

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endmodule

thanks for pointing that out kay. I did catch that, eventually

does my module look sound? it compiles just fine; working on the test 
bench now

anyone?

Maybe then someone could explain how I can connect the Gout and Eout 
outputs to the next cascaded Gin and Ein inputs with wires?

This is the code for my 4 bit comparator so far i need to figure out how 
to connect the Gout/Eout to Gin/Ein via wires. any help would be greatly 
appreciated...

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module fourbitComparator(X, Y, Ein, Gin, Eout, Gout);  //maybe 

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 input [3:0] Ein, Gin;

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 input [3:0] X, Y;

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output Eout, Gout;

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 wire Xeq0, Xeq1, Xeq2, Xeq3, Xg0, Xg1, Xg2, Xg3;

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 oneBitComparator com0(Ein[0], Gin[0], X[0], Y[0], Xeq0, Xg0);

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 oneBitComparator com1(Ein[1], Gin[1], X[1], Y[1], Xeq1, Xg1);

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 oneBitComparator com2(Ein[2], Gin[2], X[2], Y[2], Xeq2, Xg2);

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 oneBitComparator com3(Ein[2], Gin[2], X[3], Y[3], Xeq3, Xg3);

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 assign #10 Eout = (Xeq0 & Xeq1 & Xeq2 & Xeq3);

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 assign #10 Gout = (Xg3 | (Xg2 & Xeq3) | 

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 (Xg1 & Xeq3 & Xeq2) | 

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(Xg0 & Xeq3 & Xeq2 & Xeq1));

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endmodule

Have you written the testbench already?

No, could you help with the testbench plz

I think we need a for loop in it

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for (i = 0; i < 16; i = i +1) begin

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   vector = vector + i;

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end

something like this, but start with a simple testbench at first to check 
one or two Signal combinations.