Hey guys, I have this Verilog project but I don't know how to start with it, or how to do the test bench Any help is appreciated! Design a 1-bit expandable magnitude comparator that can be used as shown in the pic attached. The 1-bit expandable comparator accepts an xi input bit and a yi input bit along with gin and ein inputs (the result of the comparison of the more significant bits of X and Y) and produces gout and eout outputs to indicate that X is greater than or equal to Y. Create a Verilog behavioral dataflow model of the 1-bit comparator using a propagation delay of 10ns for both outputs. Verify your design with a testbench that exhaustively generates all possible input stimulus combinations. Once your 1-bit comparator is correct, create a 4-bit comparator as depicted above. Create a testbench to generate all possible inputs.

you can start with pseudo code and analyze the logic at first. perhaps you see it, otherwise make a truth table and you receive: g_out = x and not(y) e_out = x and y you also need a bigger truth table to take g_in and e_in in consideration: for example: g_out = (x and not(y)) or g_in the rest is verilog Basic knowledge

Thank you Klakx But I'm pretty new to Verilog and this is my 2nd project. I don't have enough knowledge yet :). I'd be thankful if anyone could help me more explaining the requirements and any codes that helps me starting this. Regards

John wrote: > Design a 1-bit expandable magnitude comparator that can be used as shown > in the pic attached. Step 1 hasabsolutelynothing to do with any HDL: pick out one of those comparators. It has 4 inputs and 2 outputs. Set up a truth table for each of the outputs. When you have done this, then maybe one can help you to transfer your truth table to Verilog... As a little hint: the truth table for e out looks like this

1 | ein gin x y eout |

2 | 0 X X X 0 | previous stage is unequal --> total result is unequal |

3 | 1 0 0 0 1 |

4 | 1 0 0 1 0 |

5 | 1 0 1 0 0 |

6 | 1 0 1 1 1 |

7 | 1 1 X X Error | not possible! input can't be greater and equal the same time |

> Create a Verilog behavioral dataflow model of the 1-bit comparator using > a propagation delay of 10ns for both outputs. What a stupid requirement. In real life you must never use a "pseudo-delay" in a functional description. Or: try it and remember me...

John just make a first try with testbench, your component and the pseudo-code and then we can help you.

guest wrote: > this project SUUUCKS! Hmmmmm, let me say it this way: YOU wanted to become an electronics engineer. And that here is a (fairly easy) job for this kind of business. It will get much more difficult later on...

:
Edited by Moderator

OK... this material is fun and gratifying... procrastinating and stressing is what sucks... can I post here here for advice on this same project?

guest wrote: > can I post here here for advice on this same project? Why not? Now you and John can try to show at least a little peace of anything instead of only saying "Do my homework"...

Thank you... I have a module built for my one bit comparator... kinda stumped on the test bench tho. here's what I have so far:

1 | module oneBitComparator (X, Y, Ein, Gin, Eout, Gout); |

2 | |

3 | input X, Y, Ein, Gin; |

4 | |

5 | output Eout, Gout; |

6 | |

7 | assign Eout = (X & Y) | (~X & ~Y); |

8 | |

9 | assign Gout = (X & ~Y); |

10 | |

11 | ```
endmodule
``` |

:
Edited by Moderator

guest wrote: > here's what I have so far: What about the inputs gin and ein? I cannot see them in your assignments, but they are in my truth table... BTW pls do it this way:

1 | [c] |

2 | verilog code |

3 | [/c] |

:
Edited by Moderator

I really wasn't sure what do do with those inputs on the 1-bit comparator... how would here be "equal or greater" (Gin, Ein) inputs when there is no previous instance of the module? I'm sorry but i'm very new to this, and I'm getting a little frantic

guest wrote: > I really wasn't sure what do do with those inputs It was the same for me. I did not know anything about this project. Then I startedthinking... > how would here be "equal or greater" (Gin, Ein) inputs when there is no > previous instance of the module? Then the "previous" result is neither greater nor is it equal. So both of them will be '0'.

Ok... was i mistaken in my assumption that x and y would be my control bits? also i was slightly confused by your ruth table showing ein true for all x and y

Lothar Miller wrote: >> how would here be "equal or greater" (Gin, Ein) inputs when there is no >> previous instance of the module? > Then the "previous" result is neither greater nor is it equal. So both > of them will be '0'. It should be set to equal, otherwise the end result can't be equal at all.

I realized that almost simultaneously as you posted it; Thank you SO much for the confirmation!! I'm thinking I need to redraw my truth table to account for all possible combinations of ein and gin, then rewrite my boolean expressions

Lattice User wrote: > It should be set to equal, otherwise the end result can't be equal at > all. Right, this can easily be seen in the truth table above. I should have had av second look...

:
Edited by Moderator

Am i correct in assuming that when gin is true gout will be true as well?

the Boolean equation I came up with is Gout= ~Ein * Gin + Ein * ~Ginx~y Eout= Ein * ~Gin * ~x * ~y + Ein * ~Ginxy

sorry i kinda botched that... this is correct Gout= ~Ein * Gin + Ein * ~Gin x * ~y Eout= Ein * ~Gin * ~x * ~y + Ein * ~Gin *x*y

:
Edited by Moderator

well my truth table and Gout equation was wrong, but i think i fixed it.

1 | module oneBitComparator (X, Y, Ein, Gin, Eout, Gout); |

2 | input X, Y, Ein, Gin; |

3 | output Eout, Gout; |

4 | assign Eout = (Ein & ~Gin & X & Y) | (Ein & ~Gin & ~X & ~Y); |

5 | assign Gout = (~Ein & Gin & X) | (Ein & ~Gin & ~Y) | (Ein & ~Gin & X & ~y); |

6 | |

7 | ```
endmodule
``` |

thanks for pointing that out kay. I did catch that, eventually

```
guest wrote in post #4040647:
> seems to be leaving out some of my asterisks. weird
Use the c and /c tags to hinder the forum sw from interpreting the * as
"bold font"...
```

does my module look sound? it compiles just fine; working on the test bench now

Maybe then someone could explain how I can connect the Gout and Eout outputs to the next cascaded Gin and Ein inputs with wires?

This is the code for my 4 bit comparator so far i need to figure out how to connect the Gout/Eout to Gin/Ein via wires. any help would be greatly appreciated...

1 | module fourbitComparator(X, Y, Ein, Gin, Eout, Gout); //maybe |

2 | |

3 | input [3:0] Ein, Gin; |

4 | |

5 | |

6 | input [3:0] X, Y; |

7 | |

8 | output Eout, Gout; |

9 | |

10 | wire Xeq0, Xeq1, Xeq2, Xeq3, Xg0, Xg1, Xg2, Xg3; |

11 | |

12 | oneBitComparator com0(Ein[0], Gin[0], X[0], Y[0], Xeq0, Xg0); |

13 | |

14 | oneBitComparator com1(Ein[1], Gin[1], X[1], Y[1], Xeq1, Xg1); |

15 | |

16 | oneBitComparator com2(Ein[2], Gin[2], X[2], Y[2], Xeq2, Xg2); |

17 | |

18 | oneBitComparator com3(Ein[2], Gin[2], X[3], Y[3], Xeq3, Xg3); |

19 | |

20 | assign #10 Eout = (Xeq0 & Xeq1 & Xeq2 & Xeq3); |

21 | |

22 | assign #10 Gout = (Xg3 | (Xg2 & Xeq3) | |

23 | |

24 | (Xg1 & Xeq3 & Xeq2) | |

25 | |

26 | (Xg0 & Xeq3 & Xeq2 & Xeq1)); |

27 | |

28 | |

29 | ```
endmodule
``` |

No, could you help with the testbench plz I think we need a for loop in it

1 | for (i = 0; i < 16; i = i +1) begin |

2 | vector = vector + i; |

3 | ```
end
``` |

something like this, but start with a simple testbench at first to check one or two Signal combinations.