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Forum: FPGA, VHDL & Verilog 1-bit expandable magnitude comparator


Author: John (Guest)
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Hey guys,
I have this Verilog project but I don't know how to start with it, or 
how to do the test bench

Any help is appreciated!

Design a 1-bit expandable magnitude comparator that can be used as shown 
in the pic attached.

The 1-bit expandable comparator accepts an xi input bit and a yi input 
bit along with gin and ein inputs (the result of the comparison of the 
more significant bits of X and Y) and produces gout and eout outputs to 
indicate that X is greater than or equal to Y.
Create a Verilog behavioral dataflow model of the 1-bit comparator using 
a propagation delay of 10ns for both outputs. Verify your design with a 
testbench that exhaustively generates all possible input stimulus 
combinations.
Once your 1-bit comparator is correct, create a 4-bit comparator as 
depicted above. Create a testbench to generate all possible inputs.

Author: Klakx (Guest)
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you can start with pseudo code and analyze the logic at first.

perhaps you see it, otherwise make a truth table and you receive:

g_out = x and not(y)
e_out = x and y

you also need a bigger truth table to take g_in and e_in in 
consideration:

for example:
g_out = (x and not(y)) or g_in

the rest is verilog Basic knowledge

Author: John (Guest)
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Thank you Klakx

But I'm pretty new to Verilog and this is my 2nd project. I don't have 
enough knowledge yet :).

I'd be thankful if anyone could help me more explaining the requirements 
and any codes that helps me starting this.
 Regards

Author: Lothar Miller (lkmiller) (Moderator)
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John wrote:
> Design a 1-bit expandable magnitude comparator that can be used as shown
> in the pic attached.
Step 1 has absolutely nothing to do with any HDL: pick out one of 
those comparators. It has 4 inputs and 2 outputs. Set up a truth table 
for each of the outputs. When you have done this, then maybe one can 
help you to transfer your truth table to Verilog...

As a little hint: the truth table for e out looks like this
  ein gin  x   y   eout
   0   X   X   X    0    |  previous stage is unequal --> total result is unequal
   1   0   0   0    1
   1   0   0   1    0
   1   0   1   0    0
   1   0   1   1    1
   1   1   X   X   Error |  not possible! input can't be greater and equal the same time

> Create a Verilog behavioral dataflow model of the 1-bit comparator using
> a propagation delay of 10ns for both outputs.
What a stupid requirement. In real life you must never use a 
"pseudo-delay" in a functional description. Or: try it and remember 
me...

Author: Klakx (Guest)
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John just make a first try with testbench, your component and the 
pseudo-code and then we can help you.

Author: guest (Guest)
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you must be in my ECE171 class... this project SUUUCKS!

Author: Lothar Miller (lkmiller) (Moderator)
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guest wrote:
> this project SUUUCKS!
Hmmmmm, let me say it this way: YOU wanted to become an electronics 
engineer. And that here is a (fairly easy) job for this kind of 
business. It will get much more difficult later on...

: Edited by Moderator
Author: guest (Guest)
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OK... this material is fun and gratifying... procrastinating and 
stressing is what sucks... can I post here here for advice on this same 
project?

Author: Lothar Miller (lkmiller) (Moderator)
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guest wrote:
> can I post here here for advice on this same project?
Why not?
Now you and John can try to show at least a little peace of anything 
instead of only saying "Do my homework"...

Author: guest (Guest)
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Thank you... I have a module built for my one bit comparator... kinda 
stumped on the test bench tho. here's what I have so far:
module oneBitComparator (X, Y, Ein, Gin, Eout, Gout);

input X, Y, Ein, Gin;

output Eout, Gout;

assign Eout = (X & Y) | (~X & ~Y);

assign Gout = (X & ~Y);

endmodule

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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guest wrote:
> here's what I have so far:
What about the inputs gin and ein?
I cannot see them in your assignments, but they are in my truth table...

BTW pls do it this way:
[c]
  verilog code
[/c]

: Edited by Moderator
Author: guest (Guest)
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I really wasn't sure what do do with those inputs on the 1-bit 
comparator... how would here be "equal or greater" (Gin, Ein) inputs 
when there is no previous instance of the module?

I'm sorry but i'm very new to this, and I'm getting a little frantic

Author: Lothar Miller (lkmiller) (Moderator)
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guest wrote:
> I really wasn't sure what do do with those inputs
It was the same for me. I did not know anything about this project. Then 
I started thinking...

> how would here be "equal or greater" (Gin, Ein) inputs when there is no
> previous instance of the module?
Then the "previous" result is neither greater nor is it equal. So both 
of them will be '0'.

Author: guest (Guest)
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Ok... was i mistaken in my assumption that x and y would be my control 
bits?

also i was slightly confused by your ruth table showing ein true for all 
x and y

Author: guest (Guest)
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i'm sorry, i meant to say select bits

Author: Lattice User (Guest)
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Lothar Miller wrote:

>> how would here be "equal or greater" (Gin, Ein) inputs when there is no
>> previous instance of the module?
> Then the "previous" result is neither greater nor is it equal. So both
> of them will be '0'.

It should be set to equal, otherwise the end result can't be equal at 
all.

Author: guest (Guest)
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I realized that almost simultaneously as you posted it; Thank you SO 
much for the confirmation!!

I'm thinking I need to redraw my truth table to account for all possible 
combinations of ein and gin, then rewrite my boolean expressions

Author: Lothar Miller (lkmiller) (Moderator)
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Lattice User wrote:
> It should be set to equal, otherwise the end result can't be equal at
> all.
Right, this can easily be seen in the truth table above. I should have 
had av second look...

: Edited by Moderator
Author: guest (Guest)
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here's the truth table i came up with:

Author: guest (Guest)
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Am i correct in assuming that when gin is true gout will be true as 
well?

Author: guest (Guest)
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the Boolean equation I came up with is

Gout= ~Ein * Gin + Ein * ~Gin  x  ~y

Eout= Ein * ~Gin * ~x * ~y + Ein * ~Gin  x  y

Author: guest (Guest)
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sorry i kinda botched that... this is correct

Gout= ~Ein * Gin + Ein * ~Gin  x *  ~y

Eout= Ein * ~Gin * ~x * ~y + Ein * ~Gin *x*y

: Edited by Moderator
Author: Kay (Guest)
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you seem to be missing 1001 on your truth table

Author: guest (Guest)
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well my truth table and Gout equation was wrong, but i think i fixed it.

module oneBitComparator (X, Y, Ein, Gin, Eout, Gout);
input X, Y, Ein, Gin;
output Eout, Gout;
 assign Eout = (Ein & ~Gin & X & Y) | (Ein & ~Gin & ~X & ~Y);
 assign Gout = (~Ein & Gin & X) | (Ein & ~Gin & ~Y) | (Ein & ~Gin & X & ~y);

endmodule


Author: guest (Guest)
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thanks for pointing that out kay. I did catch that, eventually

Author: Lothar Miller (lkmiller) (Moderator)
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guest wrote in post #4040647:
> seems to be leaving out some of my asterisks. weird
Use the c and /c tags to hinder the forum sw from interpreting the * as 
"bold font"...

Author: guest (Guest)
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does my module look sound? it compiles just fine; working on the test 
bench now

Author: guest (Guest)
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anyone?

Author: guest (Guest)
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Maybe then someone could explain how I can connect the Gout and Eout 
outputs to the next cascaded Gin and Ein inputs with wires?

Author: guest (Guest)
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This is the code for my 4 bit comparator so far i need to figure out how 
to connect the Gout/Eout to Gin/Ein via wires. any help would be greatly 
appreciated...

module fourbitComparator(X, Y, Ein, Gin, Eout, Gout);  //maybe 
 
 input [3:0] Ein, Gin;
  

 input [3:0] X, Y;

output Eout, Gout;

 wire Xeq0, Xeq1, Xeq2, Xeq3, Xg0, Xg1, Xg2, Xg3;

 oneBitComparator com0(Ein[0], Gin[0], X[0], Y[0], Xeq0, Xg0);

 oneBitComparator com1(Ein[1], Gin[1], X[1], Y[1], Xeq1, Xg1);

 oneBitComparator com2(Ein[2], Gin[2], X[2], Y[2], Xeq2, Xg2);

 oneBitComparator com3(Ein[2], Gin[2], X[3], Y[3], Xeq3, Xg3);

 assign #10 Eout = (Xeq0 & Xeq1 & Xeq2 & Xeq3);

 assign #10 Gout = (Xg3 | (Xg2 & Xeq3) | 

 (Xg1 & Xeq3 & Xeq2) | 

(Xg0 & Xeq3 & Xeq2 & Xeq1));


endmodule


Author: Dornman (Guest)
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Have you written the testbench already?

Author: John (Guest)
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No, could you help with the testbench plz

I think we need a for loop in it

Author: Klakx (Guest)
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for (i = 0; i < 16; i = i +1) begin
   vector = vector + i;
end

something like this, but start with a simple testbench at first to check 
one or two Signal combinations.

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