# Forum: FPGA, VHDL & Verilog Verilog Code for 4 32 bit numbers sorting in Ascending order

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Hello,

Can some one give verilog design and basic verilog code for designing
four 32 bit numbers sorting in Ascending order. Thanks.

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Chaitanya Bommu wrote:
> Can some one give verilog design
We are NOT doing anyones homework. Lets try it that way: YOU start with
something and we discuss what's wrong with that and what's ok.

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Lothar,

This is not my home work problem. I tried to solve using For loops like
how we will implement in C. but what I read is if we use for loops
inside the verilog code, synthesis tool will not generate a best design
net list, leading to more area of the circuit. Apart from that idea,
other designs are not striking to me. So posted, thinking that I may get
better design ideas from experienced guys. Thanks.

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It that way: a loop in a HDL (VHDL, Verilog,...) results in a
combinatoric design. Its a little bit demanding in resources, but its
easily written down. So my first attempt would be to write it down the
straight forward style, and if its "too slow" or "too big" then I would
start thinking...

I cannot help you with Verilog, because I'm VHDL, but maybe this gives
you a starting point:
http://www.lothar-miller.de/s9y/archives/78-Bubblesort.html

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//Bubble sort Version 1 - 06/17/2016

module priority_queue (clk,reset,d_en,d_in, d_out);

parameter n = 10;         //Number of inputs
parameter s = 32;         //Size of the register

input clk;
input reset;
input [s-1:0] d_in;
input d_en;
output [s-1:0] d_out;

reg [s-1:0] d_out;

reg [s-1:0] reg_in [n-1 :0];       //Input registers
reg [s-1:0] reg_out [n-1:0];       // Output registers

reg [5:0] addr_in;                 //Input register data pointer
reg [5:0] addr_out;               // Output register data pointer

reg d_sort;

reg [5:0]sort_count;

integer i,j;

always @ (posedge clk)
begin
if(reset)
begin
for(i=0; i<n; i=i+1)
reg_out [i] <= 32'd0;
d_out<= 32'd0;
d_sort<=1'b0;
sort_count <=6'd0;
end

else if (d_en)
begin
end

else if (!d_en)
begin
for (j=n-1; j>=1; j=j-1)
begin
for (i=0; i<= n-2; i=i+1)
begin
if(reg_in[i] > reg_in[i+1])      //Comparison
operation
begin
reg_in[i] <= reg_in[i+1];    // Swapping
reg_in[i+1]<= reg_in[i];     // swapping
end
reg_out[i] <= reg_in[i];         //Transfering input
reg value to output registers.
end
sort_count <= sort_count +1'b1;
end
if( sort_count == (n-1))
d_sort <=1'b1;
end

if(d_sort)
begin

end

end
endmodule}
reg [s-1:0] d_out;

reg [s-1:0] reg_in [n-1 :0];       //Input registers
reg [s-1:0] reg_out [n-1:0];       // Output registers

reg [5:0] addr_in;                 //Input register data pointer
reg [5:0] addr_out;               // Output register data pointer

reg d_sort;

reg [5:0]sort_count;

integer i,j;

always @ (posedge clk)
begin
if(reset)
begin
for(i=0; i<n; i=i+1)
reg_out [i] <= 32'd0;
d_out<= 32'd0;
d_sort<=1'b0;
sort_count <=6'd0;
end

else if (d_en)
begin
end

else if (!d_en)
begin
for (j=n-1; j>=1; j=j-1)
begin
for (i=0; i<= n-2; i=i+1)
begin
if(reg_in[i] > reg_in[i+1])      //Comparison
operation
begin
reg_in[i] <= reg_in[i+1];    // Swapping
reg_in[i+1]<= reg_in[i];     // swapping
end
reg_out[i] <= reg_in[i];         //Transfering input
reg value to output registers.
end
sort_count <= sort_count +1'b1;
end
if( sort_count == (n-1))
d_sort <=1'b1;
end

if(d_sort)
begin

end

end
endmodule

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//Bubble sort Version 1 - 06/17/2016

module priority_queue (clk,reset,d_en,d_in, d_out);

parameter n = 10;         //Number of inputs
parameter s = 32;         //Size of the register

input clk;
input reset;
input [s-1:0] d_in;
input d_en;
output [s-1:0] d_out;

reg [s-1:0] d_out;

reg [s-1:0] reg_in [n-1 :0];       //Input registers
reg [s-1:0] reg_out [n-1:0];       // Output registers

reg [5:0] addr_in;                 //Input register data pointer
reg [5:0] addr_out;               // Output register data pointer

reg d_sort;

reg [5:0]sort_count;

integer i,j;

always @ (posedge clk)
begin
if(reset)
begin
for(i=0; i<n; i=i+1)
reg_out [i] <= 32'd0;
d_out<= 32'd0;
d_sort<=1'b0;
sort_count <=6'd0;
end

else if (d_en)
begin
end

else if (!d_en)
begin
for (j=n-1; j>=1; j=j-1)
begin
for (i=0; i<= n-2; i=i+1)
begin
if(reg_in[i] > reg_in[i+1])      //Comparison
operation
begin
reg_in[i] <= reg_in[i+1];    // Swapping
reg_in[i+1]<= reg_in[i];     // swapping
end
reg_out[i] <= reg_in[i];         //Transfering input
reg value to output registers.
end
sort_count <= sort_count +1'b1;
end
if( sort_count == (n-1))
d_sort <=1'b1;
end

if(d_sort)
begin

end

end
endmodule

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verilog code for merge sort in parallel algorithm

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k.n.v.sriram wrote:
> verilog code for merge sort in parallel algorithm

can you send verilog code in quick sort

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Pleaze
i need veirlog code for quick sort
can any one share it with me
thanx

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Pleaze
i need veirlog code for quick sort
can any one share it with me
thanx

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#include <stdio.h>
main()
{
int A[20], N, Temp, i, j;
printf("\n\n\t ENTER THE NUMBER OF TERMS...: ");
scanf("%d",&N);
printf("\n\t ENTER THE ELEMENTS OF THE ARRAY...:");
for(i=1; i<=N; i++)
{
scanf("\n\t\t%d", &A[i]);
}
for(i=1; i<=N-1; i++)
for(j=i+1; j<=N;j++)
if(A[i]>A[j])
{
Temp = A[i];
A[i] = A[j];
A[j] = Temp;
}
printf("\n\tTHE ASCENDING ORDER LIST IS...:\n");
for(i=1; i<=N; i++)
printf("\n\t\t\t%d",A[i]);
}

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Can any one help in writing test bench for it

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Can anyone tell me the verilog code for finding an element in a sorted
array list

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Look at
http://dbis.cs.tu-dortmund.de/cms/de/publications/2012/sorting-networks/sorting-networks.pdf
Fig 7 for 4 inputs or Fig 11 for 8 inputs.

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C M KALAISELVI wrote:
> Can anyone tell me
Pls start a NEW thread for a NEW question!

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