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Forum: FPGA, VHDL & Verilog synthesis translate_off / on


synthesis translate_off / on
Author: Faras (Guest)
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Hi,
I have a code with the following structure

--synthesis translate_off
some sort of memory implementation/ coding
--synthesis translate_on

Please let me know if deleting this piece of code will affect the final 
output from my FPGA implementation of the code.

Thanks,
Best regards,
Faras

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Re: synthesis translate_off / on
Author: Lothar M. (lkmiller) (Moderator)
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Faras wrote:
> Please let me know if deleting this piece of code will affect the final
> output from my FPGA implementation of the code.
It shouldn't, but that depends on your synthesizer. Check out the 
corresponding documentation.

One way could also be to implement the design two times and to compare 
the output...

Or to put a necessary instruction in between such a comment sequence...

Or to remove those comments...

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