Dmtry Karlin wrote:
> A simulation shows nothing signals on out bus of the structure
Of course it schows something! What? A 'U' known as "uninitialized"?

> I have no some ideas why.
When you use a reset signal to assign start values (instead of 
initilizing them at the declaration), then you must assert this reset 
signal at the beginning of your test bench...

> I have no some ideas why.
With the simulator you can dig into each signal of each module. Then 
you can easily see, whats going on and whats going wrong...

Lothar Miller wrote:
> then you must assert this reset
> signal at the beginning of your test bench...

I did it so:

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  signal reset : std_logic :='1' ;

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  res: process

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  begin

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  for i in 0 to 100 loop

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  wait until clk='1' and clk'event;

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  end loop;

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  reset <='0';wait;

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  end process res;

Also, i created a new output signal (it is called trans).

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 trans <= transfer

,
transfer - a signal with information from output bus of CIC. In the 
simulator i saw that trans have status "U", and on output bus i have 
nulls. What is it mean? Is the CIC wrong? But i took an example from the 
book, and FIR filter also must be done correctly, because i did FIR some 
times ago and it was done correctly, and i just have taken my previous 
code with the necessary changes.

Oh, i understood.

I think you mean somethink like this:

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signal filter_in : std_logic_vector(7 downto 0):= (others =>'0');