Hello all,
I am pretty new to verilog. I need help ASAP.
I am writing a code for ALU, where I need to add a verilog
module(ADDER/SUB) in VHDL(ALU).
When I am trying to use if statement for ctrl I am getting error for
"illegal expression for if statement".
What should I do, any hel would be appreciated(as soon as possible).
The code is as follows
module add_nbit(ctr,in1,in2,inc,s1,c1);
input [3:0]ctr; // control
input [15:0]in1;
input [15:0]in2;
input inc;
output [15:0]s1;
output c1;
wire [3:0]a1=4'b0000; // reg to save the value of ctr
wire [3:0]a2=4'b0001;
genvar i;
generate for(i=0;i<1;i=i+1)begin: A
if (ctr == 0) begin // tried "0000", 4'b0000.
addnbtt A1(in1,in2,1'b0,s1,c1);
end
if (ctr == 1) begin
addnbtt A2(in1,~in2,1'b1,s1,c1);
end
end
endgenerate
endmodule
Or any other way where I can achieve this aim. In my ALU I have a
control wire which will initiate my add and subtract using verilog
module.
PLEASE HELP
Nikhil Rai
Guest
#3918479
2nd if needs to be else if.
Nikhil Rai wrote: > generate for (i=0;i<1;i=i+1) begin: Thats nonsense, you know? Your problem here is, that an if-statement can only be placed in a "always" block (as far as I can see, I'm just a VHDL guy...). This way it compiles fine:
1 | |
2 | |
3 | |
4 | |
5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | |
13 | |
14 | |
15 | |
16 | |
17 | |
18 | |
19 | |
20 | |
21 | |
22 | |
23 | |
24 | |
Just dig a little bit around. You have the internet! http://www.electrosofts.com/verilog/if_else.html http://www.asic-world.com/verilog/vbehave2.html