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Improving my code!
von Enrique Perez (Guest)

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Hello buddys!

I am working with a image sensor which delivers 4 pixels (12 bits/pixel) 
every system clock.

The pixel output of the sensor is 6 Lines x 2112 pixels. And I want to 
throw away some pixels per line according to the parameter SHIFT_COL.

For example,
- if SHIFT_COL = 1, the 1st pixel of every line should be skipped 
resulting 2111 pixels.
- if SHIFT_COL = 2, the 2 first pixels of every line should be skipped 
resulting 2110 pixels
- and so on...

Here is the code that I have already programmed. But I think that it 
could be a better coding for this issue. Any suggestion?
1
  -- Valid Pixels Management:

2
      -- Receiving 4 pixels on every clock cycle and skip some of them

3
    -- according to the parameter SHIFT_COL

4
    SHIFT_DAV  <= '0';

5
    -- New "4pixels" or The limit number of pix is not achived!                   

6
    if VID_I_DAV = '1' or (SHIFT_CNT > 0 and (SHIFT_CNT < 2112+(4*unsigned(SHIFT_COLr)))) then

7
      VID_I_CNT <= VID_I_CNT + 4;      

8
      SHIFT_SEL    <= SHIFT_SEL + 1;

9
      -- Binning 6x6 => Max. 10 pixels to shift!

10
      if FPGA_MODE_l = "100" then                                       

11
        case SHIFT_COLr is

12
          when x"0000" => -- No shifting 

13
            if SHIFT_SEL = 0 then 

14
              SHIFT_DATA_REG <= VID_I_DATA;

15
              SHIFT_DAV  <= '1';

16
              SHIFT_SEL  <= (others=>'0');

17
              SHIFT_CNT <= SHIFT_CNT + 4;

18
            end if;      

19
          when x"0001" => -- Shifting 1 column

20
            if SHIFT_SEL = 0 then               

21
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

22
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

23
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

24
            elsif SHIFT_SEL = 1 then               

25
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

26
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

27
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

28
              SHIFT_DATA_REG <= VID_I_DATA(11 downto 0) & SHIFT_PIX_REG3 & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

29
              SHIFT_DAV <= '1';

30
              SHIFT_CNT <= SHIFT_CNT + 4;

31
            elsif SHIFT_SEL = 2 then

32
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

33
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

34
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

35
              SHIFT_DATA_REG <= VID_I_DATA(11 downto 0) & SHIFT_PIX_REG3 & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

36
              SHIFT_DAV <= '1';            

37
              SHIFT_SEL   <= x"1";

38
              SHIFT_CNT <= SHIFT_CNT + 4;

39
            end if;                   

40
          when x"0002" => -- Shifting 2 columns

41
            if SHIFT_SEL = 0 then 

42
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

43
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

44
            elsif SHIFT_SEL = 1 then 

45
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

46
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

47
              SHIFT_DATA_REG <= VID_I_DATA(23 downto 0) & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

48
              SHIFT_DAV <= '1';

49
              SHIFT_CNT <= SHIFT_CNT + 4;

50
            elsif SHIFT_SEL = 2 then

51
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

52
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

53
              SHIFT_DATA_REG <= VID_I_DATA(23 downto 0) & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

54
              SHIFT_DAV <= '1';            

55
              SHIFT_SEL   <= x"1";

56
              SHIFT_CNT <= SHIFT_CNT + 4;

57
            end if;                             

58
          when x"0003" => -- Shifting 3 columns

59
            if SHIFT_SEL = 0 then 

60
              SHIFT_PIX_REG1 <= VID_I_DATA(47 downto 36);

61
            elsif SHIFT_SEL = 1 then 

62
              SHIFT_PIX_REG1 <= VID_I_DATA(47 downto 36);

63
              SHIFT_DATA_REG <= VID_I_DATA(35 downto 0) & SHIFT_PIX_REG1;

64
              SHIFT_DAV <= '1';

65
              SHIFT_CNT <= SHIFT_CNT + 4;

66
            elsif SHIFT_SEL = 2 then

67
              SHIFT_PIX_REG1 <= VID_I_DATA(47 downto 36);

68
              SHIFT_DATA_REG <= VID_I_DATA(35 downto 0) & SHIFT_PIX_REG1;

69
              SHIFT_DAV <= '1';            

70
              SHIFT_SEL   <= x"1";

71
              SHIFT_CNT <= SHIFT_CNT + 4;

72
            end if;

73
          --

74
          when x"0004" => -- Shifting 4 columns

75
            if SHIFT_SEL = 1 then 

76
              SHIFT_DATA_REG <= VID_I_DATA;

77
              SHIFT_DAV  <= '1';

78
              SHIFT_SEL  <= x"1";

79
              SHIFT_CNT <= SHIFT_CNT + 4;

80
            end if;      

81
          when x"0005" => -- Shifting 5 columns

82
            if SHIFT_SEL = 1 then               

83
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

84
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

85
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

86
            elsif SHIFT_SEL = 2 then               

87
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

88
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

89
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

90
              SHIFT_DATA_REG <= VID_I_DATA(11 downto 0) & SHIFT_PIX_REG3 & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

91
              SHIFT_DAV <= '1';

92
              SHIFT_CNT <= SHIFT_CNT + 4;

93
            elsif SHIFT_SEL = 3 then

94
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

95
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

96
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

97
              SHIFT_DATA_REG <= VID_I_DATA(11 downto 0) & SHIFT_PIX_REG3 & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

98
              SHIFT_DAV <= '1';            

99
              SHIFT_SEL   <= x"2";

100
              SHIFT_CNT <= SHIFT_CNT + 4;

101
            end if;                   

102
          when x"0006" => -- Shifting 6 columns

103
            if SHIFT_SEL = 1 then 

104
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

105
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

106
            elsif SHIFT_SEL = 2 then 

107
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

108
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

109
              SHIFT_DATA_REG <= VID_I_DATA(23 downto 0) & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

110
              SHIFT_DAV <= '1';

111
              SHIFT_CNT <= SHIFT_CNT + 4;

112
            elsif SHIFT_SEL = 3 then

113
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

114
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

115
              SHIFT_DATA_REG <= VID_I_DATA(23 downto 0) & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

116
              SHIFT_DAV <= '1';            

117
              SHIFT_SEL   <= x"2";

118
              SHIFT_CNT <= SHIFT_CNT + 4;

119
            end if;                             

120
          when x"0007" => -- Shifting 7 columns

121
            if SHIFT_SEL = 1 then 

122
              SHIFT_PIX_REG1 <= VID_I_DATA(47 downto 36);

123
            elsif SHIFT_SEL = 2 then 

124
              SHIFT_PIX_REG1 <= VID_I_DATA(47 downto 36);

125
              SHIFT_DATA_REG <= VID_I_DATA(35 downto 0) & SHIFT_PIX_REG1;

126
              SHIFT_DAV <= '1';

127
              SHIFT_CNT <= SHIFT_CNT + 4;

128
            elsif SHIFT_SEL = 3 then

129
              SHIFT_PIX_REG1 <= VID_I_DATA(47 downto 36);

130
              SHIFT_DATA_REG <= VID_I_DATA(35 downto 0) & SHIFT_PIX_REG1;

131
              SHIFT_DAV <= '1';            

132
              SHIFT_SEL   <= x"2";

133
              SHIFT_CNT <= SHIFT_CNT + 4;

134
            end if;                                         

135
          --

136
          when x"0008" => -- Shifting 8 columns

137
            if SHIFT_SEL = 2 then 

138
              SHIFT_DATA_REG <= VID_I_DATA;

139
              SHIFT_DAV  <= '1';

140
              SHIFT_SEL   <= x"2";

141
              SHIFT_CNT <= SHIFT_CNT + 4;

142
            end if;      

143
          when x"0009" => -- Shifting 9 column

144
            if SHIFT_SEL = 2 then               

145
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

146
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

147
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

148
            elsif SHIFT_SEL = 3 then               

149
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

150
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

151
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

152
              SHIFT_DATA_REG <= VID_I_DATA(11 downto 0) & SHIFT_PIX_REG3 & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

153
              SHIFT_DAV <= '1';

154
              SHIFT_CNT <= SHIFT_CNT + 4;

155
            elsif SHIFT_SEL = 4 then

156
              SHIFT_PIX_REG1  <= VID_I_DATA(23 downto 12);

157
              SHIFT_PIX_REG2  <= VID_I_DATA(35 downto 24);

158
              SHIFT_PIX_REG3  <= VID_I_DATA(47 downto 36);                            

159
              SHIFT_DATA_REG <= VID_I_DATA(11 downto 0) & SHIFT_PIX_REG3 & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

160
              SHIFT_DAV <= '1';            

161
              SHIFT_SEL   <= x"3";

162
              SHIFT_CNT <= SHIFT_CNT + 4;

163
            end if;                   

164
          when x"000A" => -- Shifting 10 columns

165
            if SHIFT_SEL = 2 then 

166
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

167
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

168
            elsif SHIFT_SEL = 3 then 

169
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

170
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

171
              SHIFT_DATA_REG <= VID_I_DATA(23 downto 0) & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

172
              SHIFT_DAV <= '1';

173
              SHIFT_CNT <= SHIFT_CNT + 4;

174
            elsif SHIFT_SEL = 4 then

175
              SHIFT_PIX_REG1 <= VID_I_DATA(35 downto 24);

176
              SHIFT_PIX_REG2 <= VID_I_DATA(47 downto 36);

177
              SHIFT_DATA_REG <= VID_I_DATA(23 downto 0) & SHIFT_PIX_REG2 & SHIFT_PIX_REG1;

178
              SHIFT_DAV <= '1';            

179
              SHIFT_SEL   <= x"3";

180
              SHIFT_CNT <= SHIFT_CNT + 4;

181
            end if;                             

182
          when others => null;

183
        end case;        

184
      end if;    

185
    end if;


Thanks anyway!

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Re: Improving my code!
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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I moved your thread from the German (uc.net) to the Englisch spoken 
forum (embdev.net).

Enrique Perez wrote:
> But I think that it could be a better coding for this issue.
For sure. This code looks like a copy-and-paste structure.

> Any suggestion?
DON'T_WRITE_ALL_THE_NAMES_IN_UPPERCASE_LETTERS! IT_MAKES_THE_ CODE 
NEARLY_UNREADABLE!

> And I want to throw away some pixels per line according to the parameter
> SHIFT_COL.
> For example,
> - if SHIFT_COL = 1, the 1st pixel of every line should be skipped
> resulting 2111 pixels.
> - if SHIFT_COL = 2, the 2 first pixels of every line should be skipped
> resulting 2110 pixels - and so on...
I would do this "skipping" during reading the line. Then its very easy: 
just don't read a value.
If you already read the line, then Skipping would be just a 
recalculation of the offset for accessing the data.

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Re: Improving my code!
von Enrique Perez (Guest)

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Ok I am sorry, I would not know where to place it

The problem is that I need to buffer a complete line in order to make 
the skipping of the pixels, and I don't have enough space in the FPGA to 
implemente a FIFO o RAM to buffer a complete line...

Any other suggestion?

Thanks

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Re: Improving my code!
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Enrique Perez wrote:
> The problem is that I need to buffer a complete line in order to make
> the skipping of the pixels
Why that?

> and I don't have enough space in the FPGA to implemente a FIFO o RAM to
> buffer a complete line...
Why not?
>> output of the sensor is 6 Lines x 2112 pixels ... (12 bits/pixel)
That means 6x2112x12 = 152064 bit. Even an ancient XC3S200 has 221,184 
bits of RAM...

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Re: Improving my code!
von Enrique Perez (Guest)

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Now the FPGA is almost 93%. I think I can't make that
 implementation in
 the FPGA.

 Anyway in the initial post ( I am very sorry). What I want to have is
 always 2112 pixels. So when for example, SHIFT_COL = 1 and the input of
 the sensor is so:
1
          Input                                      Output

2
 Pixel1 Pixel2 Pixel3 Pixel4           Pixel1   Pixel2   Pixel3   Pixel4

3
    0     1      2       3               1        2         3       4

4
    4     5      6       7               5        6         7       8

5
    8     9      10      11      =>      9        10        11      12

6
 ..                                     ..

7
 ..                                     ..

8
  2108   2109   2110  2111              2109     2110    2111    2112


 As you can see the amount of pixels is always the same: 2112.

 A lot of thanks

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Re: Improving my code!
von -gb- (Guest)

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You want to shift all values by 1 to the left?

And the leftest value from the next line N becomes the rightes in the 
line (N-1)?

What du you want to do with the Values? I think you could store the 
values in an BRAM and just offset the readaddress by one or two. The 
missing additional values in line 6 at the right can be stored 
seperatly.

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Re: Improving my code!
von Enrique Perez (Guest)

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No really, what I want to do is throw away the values according to the 
parameter SHIFT_COL. But alway I have to deliver 2112 pixels.

In my previous post, you can see that the incoming data are 4 pixels in 
parallel and I am capturing 2112 pixels always. If for example the 
content of every pixel is directly the number of the pixel (this is 
something theoretical, in reality I am going to have the pixel value 
coded in 12 bits), when SHIFT_COL = 1, I have to throw away the first 
pixels of the 4 incomming paralles pixels. When SHIFT_COL=2, I have to 
throw away 1st and 2nd pixel of the 4 incomming parallel pixels and so 
son...But always I have to provide a packet of 2112 pixels (You can 
shift the window of the sensor until 2202 pixels).

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Re: Improving my code!
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Enrique Perez wrote:
> but always I have to provide a packet of 2112 pixels
To whom? And by which means? What interface? Do you have "to deliver" it 
parallel? Or with a serial protocol pixel by pixel?

Thousands of questions. No one of them answered...

Enrique Perez wrote:
> Now the FPGA is almost 93%.
Let me say it that way: a beginner will need a much bigger FPGA due to 
not using properly components inside it. The far I can see it you can 
easily reduce that footprint: let me simply assume there is a big 
monster array somewhere in the not posted code...

> Now the FPGA is almost 93%.
Are those 93% with or without RAM blocks?

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Re: Improving my code!
von Enrique Perez (Guest)

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I have to provide 2112 pixels to the PC via Ethernet!

The sensor is delivering in parallel 4 pixels. Then I make a data 
processing where I have to do the sikiping of the pixels and a binning 
later.

It is 93% using 3 RAMs to store pixel to make the data processing.

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Re: Improving my code!
von Sigi (Guest)

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Transmitting Pixels via Ethernet means: a kind of serial process.
Receiving Pixels from Camera 4 Pix/Clock: another kind of serial
process.

Receiving Pixels: just use a simple address counter (start with 0
at line start), incremented every camera clock cycle and store
the (4) pixels in several (FPGA internal) Block RAMs.

Transmitting Pixels: use a second address counter, depending on
SHIFT_COL starting with 0,1,2,... incremented every transmitting
cycle.

Ethernet: complexity depends on the underlying protocol, but a
std. frame can be stored in an additional BlockRAM(s).

Simple Example: a Xilinx Spartan XC3S200 or XC3S250E is big
enough wrt number of BlockRAMs, the receiver/transmitter logic
needs not more than 10% of all logic recources.
The only remaining problem can be the Ethernet Protocol, but a
simple UDP-Transmitter is not so complex.

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Re: Improving my code!
von Enrique Perez (Guest)

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Thank you very much. I will test your solution on Monday!!!

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