LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

ENTITY ADC_Module_SPI IS

  PORT(

    CLK       :IN STD_LOGIC; -- external clock comes from FPGA 

    GO        : IN STD_LOGIC; -- to start the conversion by external key for example

    RESET     : IN STD_LOGIC; -- reset the system

    CS_n : OUT STD_LOGIC;  -- select line 

    SCLK : OUT STD_LOGIC; -- SPI clock for ADC conversion and transfer 

    BUSY      : IN STD_LOGIC; -- indicates if the conversion is complete or not

    EOC       : IN STD_LOGIC; -- indicate the end of conversion 

    iDOUT     : IN STD_LOGIC; -- SDOUT, data comes from the ADC 

    CNVST     : OUT STD_LOGIC; -- this line initiates the conversion

    AD_RESET  : OUT STD_LOGIC;  -- reset the ADC module

    DATA_AOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- data comes from the channel A   

    DATA_BOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)-- data comes from the channel B

  );

END ADC_Module_SPI;

ARCHITECTURE ADC_ARCH OF ADC_Module_SPI IS

TYPE ADC_STATE IS (IDLE,START,CONV_A,CONV_B,CATCH);     --Define the FSM(Finite State Machine)'s state

SIGNAL STATE_START,STATE_NEXT   : ADC_STATE;     

SIGNAL BUSY_R                : STD_LOGIC := 'Z';  --BUSY_R => to judge the rising edge of BUSY

SIGNAL EOC_R                 : STD_LOGIC := 'Z';  --EOC_R => to judge the rising edge of EOC

SIGNAL BUSY_D,EOC_D          : STD_LOGIC := 'Z';  --BUSY_D,EOC_D => to save the signal BUSY and EOC

SIGNAL DATA_ATEMP,DATA_BTEMP : STD_LOGIC_VECTOR(15 DOWNTO 0);  -- to save the AD reading data from two channel

signal go_en: STD_LOGIC;

signal iCLK: STD_LOGIC;

BEGIN

CLKPLL: SPICLK port map (CLK, iCLK);

  with go_en select

    SCLK <= iCLK when '1',  -- generate the ADC clock 

        '1'  when '0',

        '1'  when others;  

Start_ADC_proc: process(GO)

  begin  

    if(GO = '1') then 

       go_en <= '1'; -- go_en is low when the push button is pressed or reset is high 

    else 

       go_en <= '0'; -- if the push-button is not pressed, the level is high 

    end if;

end process Start_ADC_proc;

  PROCESS(iCLK,RESET) 

  VARIABLE CONV_AC  : INTEGER := 0;

  VARIABLE CONV_AFC : INTEGER := 16; -- cont the number of the cycles during the Channel A conversion

  VARIABLE CONV_BC  : INTEGER := 0;

  VARIABLE CONV_BFC : INTEGER := 16; -- cont the number of the cycles during the Channel B conversion

  BEGIN

    IF (RESET='1') THEN        -- when reset is selected 

      AD_RESET <= '1';      -- the ADC is reset 

      CONV_AC := 0;        

      CONV_BC  := 0;       

      STATE_START <= IDLE;    -- The state machine enter to the idle mode 

      DATA_ATEMP <= (OTHERS => '0');

      DATA_BTEMP <= (OTHERS => '0');

    ELSIF (iCLK'EVENT AND iCLK ='1') THEN      --when the iCLK is rising edge and do the following thing

      STATE_START <= STATE_NEXT;             

      BUSY_D <= BUSY;  -- save the actual state of the busy signal 

      EOC_D  <= EOC;   -- save the actual state of EOC signal 

      BUSY_R <= (NOT BUSY_D) AND BUSY;    -- this line is mainly for the rising edge detector for BUSY,

      EOC_R  <= (NOT EOC_D) AND EOC;      -- this line is mainly for the rising edge detector for EOC , 

      CASE STATE_START IS                   --the finite state machine with five states

        WHEN IDLE =>                   -- in the IDLE state  

          IF go_en='1' THEN          --when you start, turn off the AD_reset,and make the CNVST to high

            AD_RESET <= '0';       -- the reset ADC signal is disabled by putting it high 

            CNVST <= '1';          -- the conversion can start

            STATE_NEXT <= START;   -- the next state take the value start 

          ELSE

            STATE_NEXT <= IDLE;

          END IF;

        WHEN START =>                   -- in the Start state  when is conversion can be started 

          CNVST <='0';  

          IF BUSY_R='1' THEN          --when BUSY rising, change the state, rising edge is detected 

            STATE_NEXT <= CONV_A;    -- the CONV state is activated in the next rising edge of SCLK  

          END IF;

        WHEN CONV_A =>

          IF BUSY ='1' THEN    -- when the busy signal is always high, that means the conversion is occurring 

            IF CONV_AC = CONV_AFC THEN     

              STATE_NEXT <= CONV_B;       -- The conversion of channel A is complete, the next step is to convert the channel A    

            ELSE     

              DATA_ATEMP <= DATA_ATEMP(14 downto 0) & iDOUT;

              CONV_AC := CONV_AC +1; 

                            STATE_NEXT <= CONV_A;   

            END IF;

          END IF;

        WHEN CONV_B =>

          IF BUSY ='1' THEN    -- when the busy signal is always high, that means the conversion is occurring 

            IF CONV_BC = CONV_BFC THEN        

              STATE_NEXT <= CATCH;       -- The conversion of channel B is complete 

            ELSE     

              IF EOC_R='1' THEN    -- if busy=1 and a rising edge is detected on EOC_R, that means the channel B is ready to be converted and sent     

                  DATA_BTEMP <= DATA_BTEMP(14 downto 0) & iDOUT;

                CONV_BC := CONV_BC +1;

                STATE_NEXT <= CONV_B;             

              END IF;

            END IF;

          END IF;

        WHEN CATCH =>                         --reading the two channel data 

          DATA_AOUT <= DATA_ATEMP;

          DATA_BOUT <= DATA_ATEMP;

            STATE_NEXT <= IDLE;

      END CASE;

    END IF;

  END PROCESS;

END ADC_ARCH;