send UDP packets from FPGA

Forgot mention:

the board is ML605 evaluation board.

What level of knowledge do you have with FPGAs? Did you already 
implement some simpler hardware?

First of all, thanks for your quick responses.

Lothar Miller wrote:
> What level of knowledge do you have with FPGAs? Did you already
> implement some simpler hardware?

My experience is limited I have to say.
I have exercised vhdl for some time, starting with sinmple examples, 
which went fine.

I have worked a little on the ML605, and played a little with the clock 
and some leds.
However, in order to compute some more complex stuff, I guess I should 
get into the pc-fpga communication.

I have gone through the ML605 schematic quite a lot. I think I have 
understood most of the pins that are going to be used for an ethernet 
communication.

Schlumpf wrote:
> You have to implement a MII-Interface (or GMII or RMII) to connect
> the
> required PHY.

agreed.

> And then you have to implement a state machine that feeds the
> MII-Inteface with the frame data.

again I agree (based on other examples I have seen e.g. from opencores)

> And after that you should implement a FCS-generator that calculates and
> adds the checksum to the frame.
> If you don´t want to implement a FCS-generator you have to switch your
> NIC to promiscuous mode to avoid filtering frames with wrong FCS.
>

I think I can almost understand what the Frame check sequence generator 
should be doing. I am not very confident that I could write it myself 
though.

> with MII the data-clock is sink-driven. So your interface might be
> asynchronous to the rest of your FGPA. So you have to implement a domain
> crossing via e.g. fifo memory and you need a proper constraining of you
> wohle design.

I did not really get that last part. ( didn't google for it either)
--

In any case, I was thinking that I could implement the ethernet mac core 
from the  Xilinx Core Generator. This should save the time and workload.
But even for that, there are certain basic that I cannot understand.

The UCF file, for example. I cannot find specific info about some pins 
of the core, so I don't know how important they are, and if they should 
be connected somewhere, or just left free.

Also, for starters I would send a custom packet. I mean that I would not 
have to read+send data from memory or some random generator.

thanks again everyone!
(I am mostly self-taught, so I probably have some gaps in basic 
knowledge.)

Emil

Hello all,

I have the ML605 board. I want to send UDP packets through ethernet to 
the PC.

 - I generated the mac core through the Core generator.
 - I have the example-design files.
 - Load them in Xilinx ISE, and it seems to compile ok 
(synthesis+implement+generate programming file).
 - I program the fpga with the .bit file.
 - The PHY leds go on, and the speed config seems to work fine.
 - The DUP led is on. The TX never goes on. The RX lights up every few 
seconds, apparently due to packets from the PC (standard ethernet search 
for connection I guess).

Now the issue:

It should be enough to trigger a DIP switch to turn the packet generator 
on, but nothing happens.

Q: Assuming the core works fine, WHAT should I do to send packets to the 
PC.
The packet data can be predefined-hardcoded or time dependent.
I just need to see that I can send from the fpga.

thank you all.

Emil

Aimilianos K. wrote:
> I just need to see that I can send from the fpga.
Do you have a scope or a logic analyzer?

> - Load them in Xilinx ISE, and it seems to compile ok
> - I program the fpga with the .bit file.
Somwhere in between here is missing:
- I set up a testbench and run a simulation, which works fine.


BTW: I joined your two threads together, because they relate to the very 
same
problem.

Lothar Miller wrote:
> Aimilianos K. wrote:
>> I just need to see that I can send from the fpga.
> Do you have a scope or a logic analyzer?
>

I do not understand.
I think I have neither, but also I probably don't know what they are.

>> - Load them in Xilinx ISE, and it seems to compile ok
>> - I program the fpga with the .bit file.
> Somwhere in between here is missing:
> - I set up a testbench and run a simulation, which works fine.
>

I understand that. However: Can I just simulate ethernet communication 
inside ISIM?

Of course I should try, but I have doubts for the ability of the 
simulation to certify that such a design would work.
In any case, I am not doubting your expertise.

> BTW: I joined your two threads together, because they relate to the very
> same
> problem.

Ok. I will keep it in mind next time. Thanks.

Aimilianos K. wrote:
> Can I just simulate ethernet communication inside ISIM?
You do not simulate the complete Ethernet communication. You just 
simulate the communication to the phy on the MII interface. Just to have 
a look whether the MAC and the example design work at all...

>> Do you have a scope or a logic analyzer?
> I do not understand.
With an oscilloscope you could see whether theres any activity on the 
MII interface. With a logic analyzer you could trace down to the 
telegram level. without any (and without a working simulation) you are 
virtually blind and can react just on third party information like 
flickering LEDs...

Lothar Miller wrote:
> Aimilianos K. wrote:
>> Can I just simulate ethernet communication inside ISIM?
> You do not simulate the complete Ethernet communication. You just
> simulate the communication to the phy on the MII interface. Just to have
> a look whether the MAC and the example design work at all...

If I get it right:
The simulation will only show whether or not there is data going to the 
TX ports?

(still something).

I will try it.

---

Isn't there any easier way to send data through ethernet?

Aimilianos K. wrote:
> Isn't there any easier way to send data through ethernet?
You could do it from your PC...

> Isn't there any easier way to send data through ethernet?
Ethernet is a abstract high level medium. So there is no simple way to 
get it running as easy as eg. a RS232 communication...

Lothar Miller wrote:
> Somwhere in between here is missing:
> - I set up a testbench and run a simulation, which works fine.

I am trying to make it work in a testbench.

However I think I need to implement the LVDS somehow, and I cannot 
understand.
Obviously it can't be just two clocks with phase difference.

Q: How can I simulate LVDS in the testbench?

thank you Lothar and everyone!

Aimilianos K. wrote:
> Q: How can I simulate LVDS in the testbench?
This is the wrong abstraction level for the testing the behavior of 
your interface!

As Lothar Miller wrote:
>> You do not simulate the complete Ethernet communication. You just
>> simulate the communication to the phy on the MII interface.
See http://en.wikipedia.org/wiki/Media_Independent_Interface
And so the interface is only 16 digital signals connected between the 
FPGA and the PHY. Because the PHY is a device with a datasheet you can 
implement this interface by the PHYs datasheet. At this behavioral level 
there is no need of LVDS or similar.