Lothar Miller wrote:
> insert it into your posts text surrounded by the vhdl tokens
1 | [vhdl] VHDL Code [/vhdl]
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Ok, I did it for you. Now lets start:
Never use both of the arithmetic libraries together:
1 | use ieee.numeric_std.all;
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2 | use ieee.std_logic_unsigned.all;
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Use the numeric_std and the conversions in it only!
Otherwise you may have double defined datatypes in your VHDL code.
This could be written gerneric in one line:
1 | for i in 1 to shift loop
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2 | append(i) := '0';
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3 | end loop;
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Do it this way:
1 | append := (others=>'0');
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Where is this "15" from?
1 | variable V: std_logic_vector((shift+15) downto 0);
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And why should you try to shift a 16 bit vector 65536 times?
1 | variable shift:integer range 0 to 65535:= to_integer(unsigned(B));
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The actual problem is this here:
This here is not possible, because shift must be constant because (x
downto y) only accept constants. But shift is evaluated out of B, and
B istn't constant:
1 | variable shift:integer range 0 to 65535:= to_integer(unsigned(B));
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2 | variable append: std_logic_vector (shift downto 1); -- shift must be constant!
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And also the begin and the end of a loop must be constant:
1 | for i in 0 to shift loop
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Why do you do the thing so circiutous?
You must look at the problem not with a programmers "software view", but
with a sense for the hardware you want. So there is the quuestion: what
is a barrel shifter? Fairly easy: a big multiplexer.
And after knowing what you need you must describe this big multiplexer.
Thats all.
You nearly got the way by shifting the input in a bigger vector and
cutting out the slice you want (thats the multiplexer actually).
So first is to say: a 16 bit vector can be shifted either 16 bits the
one or 16 the other way. Then it may look like this:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity barrelshifter is
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6 | port(A: IN std_logic_vector(15 downto 0);
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7 | B: IN std_logic_vector(3 downto 0);
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8 | D: IN std_logic;
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9 | ShiftOut: OUT std_logic_vector (15 downto 0));
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10 | end barrelshifter;
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11 |
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12 | architecture behavior of barrelshifter is
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13 | begin
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14 |
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15 | process (A,B,D)
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16 | variable s : integer range 0 to 15;
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17 | variable r : std_logic_vector(15 downto 0);
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18 | begin
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19 | s := to_integer(unsigned(B));
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20 | r := (others=>'0');
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21 | for i in 0 to 15 loop
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22 | if D = '1' then r(s+i) := A(i);
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23 | else r(i) := A(i+s);
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24 | end if;
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25 | if (s+i =15) then exit; end if;
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26 | end loop;
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27 | ShiftOut <= r;
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28 | end process;
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29 | end behavior;
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Its fine, I tested it with this TB:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity tb_barrelshifter is
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6 | end tb_barrelshifter;
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7 |
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8 | architecture structure of tb_barrelshifter is
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9 | component barrelshifter
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10 | port(A: IN std_logic_vector(15 downto 0);
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11 | B: IN std_logic_vector(3 downto 0);
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12 | D: IN std_logic;
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13 | ShiftOut: OUT std_logic_vector(15 downto 0));
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14 | end component;
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15 |
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16 | signal B: std_logic_vector(3 downto 0);
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17 | signal A,ShiftOut: std_logic_vector(15 downto 0);
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18 | signal D: std_logic;
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19 |
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20 | begin
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21 | DUT: barrelshifter port map(A,B,D,ShiftOut);
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22 |
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23 | process
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24 | begin
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25 | for i in 0 to 15 loop
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26 | A<= x"8001";
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27 | B<= std_logic_vector(to_unsigned(i,4));
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28 | D <='0';
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29 | wait for 20 ns;
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30 | end loop;
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31 |
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32 | wait for 200 ns;
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33 |
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34 | for i in 0 to 15 loop
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35 | A<= x"8001";
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36 | B<= std_logic_vector(to_unsigned(i,4));
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37 | D <='1';
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38 | wait for 20 ns;
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39 | end loop;
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40 |
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41 | wait for 200 ns;
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42 |
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43 | end process;
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44 | end structure;
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source.jpg
(150 KB)
test_bench.jpg
(140 KB)
error.jpg
(150 KB)
