EmbDev.net

Forum: FPGA, VHDL & Verilog remains a black-box since it has no binding entity


von Kim (Guest)


Rate this post
0 useful
not useful
Hello, I have a problem programming vhdl. The  message I am getting is 
HDLCompiler:89 remains a black-box since it has no binding entity.

How can this issue be solved?

Thanks for your help.

von Lothar M. (lkmiller) (Moderator)


Rate this post
1 useful
not useful
Kim wrote:
> How can this issue be solved?
No answer is possible because your code (that one producing the error) 
is not attached...

von kim (Guest)


Rate this post
0 useful
not useful
Hi this is the code I am having problems with...
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
library work;
5
use work.convert_pack.all;
6
7
entity test is
8
    Port ( 
9
   clk_o : out  STD_LOGIC;
10
   output : inout std_logic;
11
   clk : inout std_logic;
12
   index : inout std_logic_vector(6 downto 0)
13
   
14
   );
15
end test;
16
17
architecture rtl of test is
18
19
20
    component ntest
21
        PORT(
22
     output  : out std_logic;
23
     clk : in std_logic;
24
    index : in  std_logic_vector(6 downto 0)
25
      );
26
    END COMPONENT;
27
28
  
29
30
BEGIN
31
32
   bla: ntest  
33
  PORT MAP (
34
  clk => clk,
35
  index  => index,
36
  output => output
37
  );       
38
39
40
   clk_process :process(clk, index, output)
41
   begin
42
  
43
  
44
  clk <= not(clk);
45
  
46
  if (rising_edge(clk) and clk = '1') then
47
  index <= u2slv(slv2u(index)+1);
48
  end if;
49
  
50
  if  slv2u(index)= 89 and output = '1'then --
51
  index <= (others => '0');
52
  output <='0';
53
  end if;
54
  
55
  if  slv2u(index) = 34 and output = '0'then --
56
  index <= (others => '0');
57
  output <='1';
58
  end if;
59
60
clk_o <= output;
61
62
end process;
63
64
65
66
end rtl;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


Rate this post
1 useful
not useful
Pls use the VHDL tags. How to use them? Its in the edit box for the text 
input:
1
Reply
2
Rules — please read before posting
3
    Post long source code as attachment, not in the text
4
    Posting advertisements is forbidden.
5
6
Formatting options
7
    [vhdl]VHDL code[/vhdl]
8
9
...


This is a VERY unusual way to generate a "clock":
1
 clk_process :process(clk, index, output)
2
 begin
3
  clk <= not(clk);
4
  if (rising_edge(clk) and clk = '1') then
5
     ...
Where did you find such a piece of code? Is it your own? How do others 
generate a clock? Why do they do it much different?

Kim wrote:
> remains a black-box since it has no binding entity.
Wheres the entity of ntest? Is it included to the project?

von sia (Guest)


Rate this post
0 useful
not useful
what does this error mean ?

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
sia wrote:
> what does this error mean ?
An entity is missing in the project files list.

> what does this error mean ?
What particular error in conjunction with what design?

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.