remains a black-box since it has no binding entity

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library work;

use work.convert_pack.all;

entity test is

    Port ( 

   clk_o : out  STD_LOGIC;

   output : inout std_logic;

   clk : inout std_logic;

   index : inout std_logic_vector(6 downto 0)

   );

end test;

architecture rtl of test is

    component ntest

        PORT(

     output  : out std_logic;

     clk : in std_logic;

    index : in  std_logic_vector(6 downto 0)

      );

    END COMPONENT;

BEGIN

   bla: ntest  

  PORT MAP (

  clk => clk,

  index  => index,

  output => output

  );       

   clk_process :process(clk, index, output)

   begin

  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then

  index <= u2slv(slv2u(index)+1);

  end if;

  if  slv2u(index)= 89 and output = '1'then --

  index <= (others => '0');

  output <='0';

  end if;

  if  slv2u(index) = 34 and output = '0'then --

  index <= (others => '0');

  output <='1';

  end if;

clk_o <= output;

end process;

end rtl;