Hi guys,

I am having problems with my program and wonder if anyone can help me 
out.
The errormessage i am getting is:
ERROR:HDLCompiler:1171 - Line 30: Illegal recursive instantiation of 
test(rtl)

does anyone know how to solve this?


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
library work;
use work.convert_pack.all;

entity test is --line 30
    Port (
   clk_o : out  STD_LOGIC;
   output : inout std_logic;
   clk : inout std_logic;
   index : inout  std_logic_vector(0 downto 0)

   );
end test;

architecture rtl of test is


    component test
        PORT(
     output  : out std_logic;
     clk : in std_logic;
    index : in  std_logic_vector(0 downto 0)
      );
    END COMPONENT;



BEGIN

   bla: test
  PORT MAP (
  clk => clk,
  index  => index,
  output => output
  );


   clk_process :process(clk, index, output)
   begin


  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then
  index <= u2slv(slv2u(index)+1);
  end if;

  if  index = 89 and output = '1'then --
  index <= (others => '0');
  output <='0';
  end if;

  if  index = 34 and output = '0'then --
  index <= (others => '0');
  output <='1';
  end if;

clk_o <= output;

end process;



end rtl;





PS: I am working on a Spartan-6 Atlys Board in case this information is 
needed.