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Forum: FPGA, VHDL & Verilog Illegal recursive instantiation


von Iluvatar (Guest)


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Hi guys,

I am having problems with my program and wonder if anyone can help me 
out.
The errormessage i am getting is:
ERROR:HDLCompiler:1171 - Line 30: Illegal recursive instantiation of 
test(rtl)

does anyone know how to solve this?


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
library work;
use work.convert_pack.all;

entity test is --line 30
    Port (
   clk_o : out  STD_LOGIC;
   output : inout std_logic;
   clk : inout std_logic;
   index : inout  std_logic_vector(0 downto 0)

   );
end test;

architecture rtl of test is


    component test
        PORT(
     output  : out std_logic;
     clk : in std_logic;
    index : in  std_logic_vector(0 downto 0)
      );
    END COMPONENT;



BEGIN

   bla: test
  PORT MAP (
  clk => clk,
  index  => index,
  output => output
  );


   clk_process :process(clk, index, output)
   begin


  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then
  index <= u2slv(slv2u(index)+1);
  end if;

  if  index = 89 and output = '1'then --
  index <= (others => '0');
  output <='0';
  end if;

  if  index = 34 and output = '0'then --
  index <= (others => '0');
  output <='1';
  end if;

clk_o <= output;

end process;



end rtl;





PS: I am working on a Spartan-6 Atlys Board in case this information is 
needed.

von Tobias L. (murxwitz)


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Your Toplevel Entity and the component you try to instantiate are both 
named test, so you have to rename one
1
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
use IEEE.STD_LOGIC_ARITH.ALL;
5
use IEEE.STD_LOGIC_SIGNED.ALL;
6
library work;
7
use work.convert_pack.all;
8
9
entity test_top is --line 30
10
    Port (
11
   clk_o : out  STD_LOGIC;
12
   output : inout std_logic;
13
   clk : inout std_logic;
14
   index : inout  std_logic_vector(0 downto 0)
15
16
   );
17
end test_top;
18
19
architecture rtl of test_top is
20
21
22
    component test
23
        PORT(
24
     output  : out std_logic;
25
     clk : in std_logic;
26
    index : in  std_logic_vector(0 downto 0)
27
      );
28
    END COMPONENT;
29
30
31
32
BEGIN
33
34
   bla: test
35
  PORT MAP (
36
  clk => clk,
37
  index  => index,
38
  output => output
39
  );
40
41
42
   clk_process :process(clk, index, output)
43
   begin
44
45
46
  clk <= not(clk);
47
48
  if (rising_edge(clk) and clk = '1') then
49
  index <= u2slv(slv2u(index)+1);
50
  end if;
51
52
  if  index = 89 and output = '1'then --
53
  index <= (others => '0');
54
  output <='0';
55
  end if;
56
57
  if  index = 34 and output = '0'then --
58
  index <= (others => '0');
59
  output <='1';
60
  end if;
61
62
clk_o <= output;
63
64
end process;
65
66
end rtl;

should work (not tested)

PS: don't use the obsolete
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

: Edited by User
von Iluvatar (Guest)


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thanks for the hint, i got now this error message:
Line 71: found '0' definitions of operator "=", cannot determine exact 
overloaded matching definition for "="


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pack.all;

entity test is
    Port (
   clk_o : out  STD_LOGIC;
   output : inout std_logic;
   clk : inout std_logic;
   index : inout  std_logic_vector(0 downto 0)

   );
end test;

architecture rtl of test is


    component ntest
        PORT(
     output  : out std_logic;
     clk : in std_logic;
    index : in  std_logic_vector(0 downto 0)
      );
    END COMPONENT;



BEGIN

   bla: ntest
  PORT MAP (
  clk => clk,
  index  => index,
  output => output
  );


   clk_process :process(clk, index, output)
   begin


  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then
  index <= u2slv(slv2u(index)+1);
  end if;

  if  index = 89 and output = '1'then --line 71
  index <= (others => '0');
  output <='0';
  end if;

  if  index = 34 and output = '0'then --
  index <= (others => '0');
  output <='1';
  end if;

clk_o <= output;

end process;



end rtl;

von Lothar M. (lkmiller) (Moderator)


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Pls use the VHDL tags (to be found in the "Formatting options" a few 
lines under "Reply Rules — please read before posting")!

Iluvatar wrote:
> thanks for the hint, i got now this error message:
> Line 71:  found '0' definitions of operator "=", cannot determine exact
> overloaded matching definition for "="
1
  if index = 89 and output = '1' then
VHDL has a very strict data type handling. You cannot compare a vector 
with an integer. Those two are COMPLETELY different. And therefore the 
operator '=' don't "know" hao to handle those two operands.
Two solutions:
1. You must compare the same data types
2. you must overload the '=' funktion (yes, its only a function in VHDL)

This here is a stupid lazy "trick":
1
output : inout std_logic;
2
clk : inout std_logic;
3
index : inout std_logic_vector(0 downto 0)
Every beginner thinks to be neat defining ports as inout to read them 
"back". But this is the most easy way to dig holes in the structure of a 
VHDL description. Beeing your boss or your teacher I would degrade you 
for that...  :-o

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