Hi I am stuck with a problem in vhdl and hope someone can help me solving this. I am trying to implement a driver on a Atlys Spartan-6 board to read out data which comes in via HDMI. I allready located the variable (std_logic_vector(23 downto 0)) which carries the signal i want to export from the Atlys driver. The new driver has as input a variable (unsigned(7 downto 0)) in which only the adress of my datastream is inserted. My problem now is to set a pointer between those two variables. I believe I somehow have to define my vector as access type, but however i am trying to do this, it won't work. I hope someone can give me a hint how to solve this.
Hi, Adressing some physical connections in your FPGA won't work, so I guess your Is-Access-approach won't work as expected. So what do you want to achieve? Do you want to extract a value from your 24-Bit input signal (e.g. input(15 downto 8) ) and assign this 8 to some other module? What I'm talking about:
entity test is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (24 downto 0);
output : out STD_LOGIC_VECTOR( 7 downto 0) );
architecture Behavioral of test is
if RISING_EDGE( clk ) then
output <= input(15 downto 8);
Is this approximately what you're trying to do? Note that I didn't care about type conversions like:
foobar <= std_logic_vector( resize( output(7 downto 0), output'length) );
Sorry, if I can't help you further, my HDL has gotten a bit rusty in the last 5 years...
Thank you for your help so far, but in this case you are describing only a quarter of the information is beeing sent. Here is a little part of the drivers code: library work; use work.dds_pack.all; use work.convert_pack.all; entity ws2812_LED_chain_driver is generic ( SYS_CLK_RATE : real := 50000000.0; -- underlying clock rate ADR_BITS : natural := 8; -- Must equal or exceed BIT_WIDTH(N_LEDS)+2. N_LEDS : natural := 8 -- Number of LEDs in chain ); port ( -- System Clock, Reset and Clock Enable sys_rst_n : in std_logic; sys_clk : in std_logic; sys_clk_en : in std_logic; -- Selection of color information c_adr_o : out unsigned(ADR_BITS-1 downto 0); c_dat_i : in unsigned(7 downto 0); -- Output sdat_o : out std_logic ); end ws2812_LED_chain_driver; As you can see the color information is a vector[7 downto 0]. The datastream for the input is a STD_LOGIC_VECTOR (23 downto 0), for each color 8 bit are needed. I am quite a VHDL noobie but i cant believe that there is no way to adress this 24-bit Variable directly. I mean otherwise the entire driver doesnt work.
Kim wrote: > > I am quite a VHDL noobie but i cant believe that there is no way to > adress this 24-bit Variable directly. I mean otherwise the entire driver > doesnt work. You are thinking in software terms. VHDL is a hardware description language and not a programming language. What you call a "driver" is the description of a hardware module which is build inside the FPGA by the synthesiser. The STD_LOGIC_VECTOR is just a bunch of connection wires to connect this module, and not some memory variable with a address.
Kim wrote: > Thank you for your help so far, but in this case you are > describing only > a quarter of the information is beeing sent. Well, I hoped to avoid confusion by omitting additional signals - I guess that's the task of example code. > Here is a little part of the drivers code: > > library work; > use work.dds_pack.all; > use work.convert_pack.all; > > entity ws2812_LED_chain_driver is > generic ( > SYS_CLK_RATE : real := 50000000.0; -- underlying clock rate > ADR_BITS : natural := 8; -- Must equal or exceed > BIT_WIDTH(N_LEDS)+2. > N_LEDS : natural := 8 -- Number of LEDs in chain > ); > port ( > > -- System Clock, Reset and Clock Enable > sys_rst_n : in std_logic; > sys_clk : in std_logic; > sys_clk_en : in std_logic; > > -- Selection of color information > c_adr_o : out unsigned(ADR_BITS-1 downto 0); > c_dat_i : in unsigned(7 downto 0); > > -- Output > sdat_o : out std_logic > ); > end ws2812_LED_chain_driver; > > As you can see the color information is a vector[7 downto 0]. > The datastream for the input is a STD_LOGIC_VECTOR (23 downto 0), for > each color 8 bit are needed. > > I am quite a VHDL noobie but i cant believe that there is no way to > adress this 24-bit Variable directly. I mean otherwise the entire driver > doesnt work. As Lattice User already mentioned, your HDL synthesis generates you a Logic circuit, in especially a set of logical functions that gets connected by some switching logic. A 'Signal' in HDL is a physical wire connecting subcircuits. How do you want to address wires? You're working on register-transfer-level, no memory-like-addressing is available here using VHDL. If you still can't imagine, how HDL works: Try to build a circuit with 74*-NAND-ICs in a breadboard - how would you solve your problem there. You could also use the Schematic Editor to get some understanding about the results you're getting from your synthesis. In order to solve your task, you probably have to describe your own address decoding logic that maps the memory address to a value. That means you have to write your own indirection logic, if the design you're using doesn't already have such component.
db8fs wrote: > A 'Signal' in HDL is a physical wire connecting subcircuits. A signal (or even a variable) in VHDL may be a register also: just involve a clock to get a register. And it may be a latch, mostly a undesired one...
Lothar Miller wrote: > db8fs wrote: >> A 'Signal' in HDL is a physical wire connecting subcircuits. > A signal (or even a variable) in VHDL may be a register also: just > involve a clock to get a register. And it may be a latch, mostly a > undesired one... You're absolutely right, of course the synthesizer has to resolve time-dependencies and will create sequential logic for it. My intention was to point out the different layers of computer architecture and the differences in designing for the algorithmical level and for sub-algorithmical levels like the Register-Transfer-Level. Unfortunately the hardware design gets confused by things like SystemC or other HighLevel-Synthesis-Tools. They promise to be easy and usable like ordinary programming languages, but they still need to be used with the mind or the view of a hardware designer placing logic circuits. And even VHDL/Verilog gives the user a lot of possibilities with the risk for the beginner of creating non-sythesizable descriptions.