is not declared

library IEEE;                                                                      

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--

entity system_core is

  port( I_SYSTEM_CLK_50M : in std_logic;

      I_SYSTEM_RST    : in std_logic;

      O_SYSTEM_CLK_1HZ : inout std_logic;

      O_SYSTEM_SEG_OUT : out std_logic_vector (7 downto 0):=(others=>'0')

      );

end system_core;

entity div_50M is

  port( I_CLK_50M : in std_logic;

      I_RST     : in std_logic;

      O_1HZ     : out std_logic);

end div_50M;

entity seven_seg is

  port ( I_EVENT_1HZ : in std_logic;

       SEG_OUT : out std_logic_vector (7 downto 0):=(others=>'0'));

end seven_seg;

Parsing architecture <arc0> of entity <system_core>.

Parsing entity <div_50M>.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 35: <std_logic> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 36: <std_logic> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 37: <std_logic> is not declared.

ERROR:HDLCompiler:854 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 34: Unit <div_50m> ignored due to previous errors.

Parsing architecture <arc1> of entity <div_50m>.

ERROR:HDLCompiler:374 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 41: Entity <div_50m> is not yet compiled.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 42: <std_logic> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 43: <std_logic_vector> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 51: <l_led_ctr> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 53: <l_led> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 54: <l_led_ctr> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 52: <l_led_ctr> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 56: <l_led_ctr> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 50: <i_rst> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 49: <i_clk_50m> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 60: <o_1hz> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 47: <i_clk_50m> is not declared.

Parsing entity <seven_seg>.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 66: <std_logic> is not declared.

ERROR:HDLCompiler:69 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 67: <std_logic_vector> is not declared.

ERROR:HDLCompiler:854 - "C:\Users\BAT\Desktop\xilinx\Exapmles\vhdl_test\first_module.vhd" Line 65: Unit <seven_seg> ignored due to previous errors.

library IEEE;                                                                      

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--

entity system_core is

  port( I_SYSTEM_CLK_50M : in std_logic;

      I_SYSTEM_RST    : in std_logic;

      O_SYSTEM_CLK_1HZ : inout std_logic;

      O_SYSTEM_SEG_OUT : out std_logic_vector (7 downto 0):=(others=>'0')

      );

end system_core;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--

entity div_50M is

  port( I_CLK_50M : in std_logic;

      I_RST     : in std_logic;

      O_1HZ     : out std_logic);

end div_50M;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

--

entity seven_seg is

  port ( I_EVENT_1HZ : in std_logic;

       SEG_OUT : out std_logic_vector (7 downto 0):=(others=>'0'));

end seven_seg;