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#3743861
Hi, I want to connect 2 components in vhdl but I have some trouble to write the code because of multiple connections in port map. The output of the component is a real_vector(0 to 3) and is connected to multiple outputs of an other component as below: fast_anlog_in(0) => adc1_vinp(0), adc2_vinp(0) fast_anlog_in(1) => adc1_vinn(0), adc1_vinp(1), adc2_vinn(0), adc2_vinp(1) fast_anlog_in(2) => adc3_vinp(0) fast_anlog_in(3) => adc3_vinn(0), adc3_vinp(1) What is the good way to proceed ? Thank you !
