please help edge detection

Mark Jomari wrote:
> why this is happening?
What happens and what did you expect instead?
What way do you get from one to the other?

Read your own post as everybody here must read it: without ANY knowledge 
about your problem. You will see: nobody cannot understand anything!


And: what has your problem to do with FPGAs, Asics or other programmable 
logic?
If so: what platform? What hardware? What toolchain?

im sorry,. what i mean is,. on the left side is the sobel edge 
detection, and on the right side is the grayscale input,,
,. why the output looks like that?

i think so,. because in my simulation in modelsim, the result of the 
sobel edge detection takes 7 posedge clk before getting the magnitude,, 
how can i control the delay of the output of vga,?

i use pipelining in this program,, as of now, it is working correctly,, 
one question,, hows the clken works?