Hi:
I'm trying to control a servomotor HS-645MG with the Altera FPGA DE0
using VHDL. According to my limited knowledge (and according to other
programmers) these are the code for frequency dividing and pwm:
Frequency divider:
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity clk64kHz is
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5 | Port (
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6 | clk : in STD_LOGIC;
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7 | reset : in STD_LOGIC;
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8 | clk_out: out STD_LOGIC
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9 | );
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10 | end clk64kHz;
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11 |
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12 | architecture Behavioral of clk64kHz is
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13 | signal temporal: STD_LOGIC;
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14 | signal counter : integer range 0 to 4999 := 0;
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15 | begin
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16 | freq_divider: process (reset, clk) begin
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17 | if (reset = '1') then
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18 | temporal <= '0';
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19 | counter <= 0;
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20 | elsif rising_edge(clk) then
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21 | if (counter = 4999) then
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22 | temporal <= NOT(temporal);
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23 | counter <= 0;
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24 | else
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25 | counter <= counter + 1;
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26 | end if;
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27 | end if;
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28 | end process;
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29 |
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30 | clk_out <= temporal;
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31 | end Behavioral;
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PWM
1 | library IEEE;
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2 |
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3 | use IEEE.STD_LOGIC_1164.all;
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4 | use IEEE.STD_LOGIC_unsigned.all;
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5 |
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6 | -----------------------------------------------------
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7 |
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8 | entity pwm is
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9 | port(
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10 | clr : in std_logic;
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11 | clk : in std_logic;
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12 | duty : in std_logic_vector (7 downto 0);
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13 | period : in std_logic_vector (7 downto 0);
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14 | pwm : out std_logic
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15 | );
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16 |
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17 | end pwm;
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18 |
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19 | -----------------------------------------------------
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20 |
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21 | architecture pwm of pwm is
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22 |
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23 | signal count : std_logic_vector(7 downto 0);
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24 |
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25 | begin
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26 |
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27 | cnt: process(clk, clr) -- 4 bit counter
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28 | begin
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29 | if clr = '1' then
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30 | count <= "00000000";
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31 | elsif clk'event and clk = '1' then
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32 | if count = period -1 then
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33 | count <= "00000000";
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34 | else
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35 | count <= count +1;
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36 | end if;
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37 | end if;
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38 | end process cnt;
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39 |
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40 | pwmout: process(count, duty)
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41 | begin
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42 | if count < duty then
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43 | pwm <= '1';
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44 | else
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45 | pwm <= '0';
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46 | end if;
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47 | end process pwmout;
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48 |
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49 | end pwm;
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Top-design code
1 | -----------------------------------------------------
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2 |
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3 | library IEEE;
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4 |
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5 | use IEEE.STD_LOGIC_1164.all;
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6 | use IEEE.STD_LOGIC_unsigned.all;
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7 |
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8 | -----------------------------------------------------
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9 |
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10 | entity pwm_top is
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11 | port(
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12 | clr : in std_logic;
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13 | clk : in std_logic;
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14 | duty : in std_logic_vector (7 downto 0);
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15 | pwm : out std_logic
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16 | );
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17 |
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18 | end pwm_top;
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19 |
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20 | -----------------------------------------------------
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21 |
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22 | architecture pwm_top of pwm_top is
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23 |
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24 | signal new_clock : std_logic;
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25 |
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26 | begin
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27 |
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28 | clk_div: entity work.clk64kHz
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29 | port map(
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30 | clk => clk, reset => '0', clk_out => new_clock);
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31 |
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32 | Pulse: entity work.pwm
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33 | port map(
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34 | clr => clr, clk => new_clock, duty => duty, period => "11001000", pwm => pwm);
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35 |
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36 | end pwm_top;
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Described with my own words, the frequency is divided by a 5000 factor
which yields to a new frequency of 10000Hz (0.1ms). Then the period of
the pwm is assigned as 200 so the frequency of pwm will be 20ms and the
duty cycle will be controlled with the DE0 built-in switches.
Unfortunately this doesnt work very well when the servo is connected,
for example, if the duty cycle is 0.5ms the servo is supposed to moved
to one end but instead, it seems to take a 45º position. For every other
position, the servo also moves but it doesnt move accordingly to the
duty cycle.
I have tested the servo with an arduino uno and works wonders.
What could be the problem?
Any ideas are welcomed.
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