multiplication real with std_logic vector

sebgimi wrote:
> How can I fix it ?
Is this code only for simulation?

> Below the part of code I wrote:
What packages/libraries do you use (the first few lines of your HDL 
code)?

sebgimi wrote:
> use ieee.numeric_std.all;
Then you cannot multiply two std_logic_vectors. Use signed or unsigned 
vectors instead.

BTW: What data type is data?

sebgimi wrote:
> I'm a little bit lost with all these types...
Have a look there (try Google translator,its German):
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std
And then remind: in the numeric_std the multiplication is only defined 
for signed and unsigned vectors.

Then your calculation must look this way

1

 data <= std_logic_vector( signed(data) * to_signed(integer(1.5*8192.0),data'length) );

But why not definig data itself as a signed vector?
The result of a vector multiplication is twice the with of a single 
vector (or the sum of the bits of both).

I would do the calculation in integer. Then you don't have to hassle 
aruond with vector lengths:

1

 data <= std_logic_vector(to_signed(to_integer(signed(data)) * integer(1.5*8192.0), data'length));

sebgimi wrote:
> declare data as a signed vector of 28 bits and write the line of
> calculation above ?
It you do so, this will be enough:

data <= to_signed(to_integer(data) * integer(1.5*8192.0), data'length);