Hi everyone! I want to multiply a std_logic_vector value (14 bits) with a real number. But there is a problem of size of data I think. The compiler show me these errors: "operator argument type mismatch" Below the part of code I wrote:

1 | data <= data * std_logic_vector(to_signed(integer(1.5*8192.0),data'length)) |

2 | when VREF_ADC_COM_value = 0.6 else |

3 | |

4 | data * std_logic_vector(to_signed(integer(1.2*8192.0),data'length)) |

5 | when VREF_ADC_COM_value = 0.75 else |

6 | |

7 | data; |

How can I fix it ? Thank you!

sebgimi wrote: > How can I fix it ? Is this code only for simulation? > Below the part of code I wrote: What packages/libraries do you use (the first few lines of your HDL code)?

Yes it's only for simulation. The libraries I use: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

sebgimi wrote: > use ieee.numeric_std.all; Then you cannot multiply two std_logic_vectors. Use signed or unsigned vectors instead. BTW: What data type isdata?

Lothar Miller wrote: > BTW: What data type is data? data is a std_logic_vector(13 downto 0) So, do I have to create an other signal "data unsigned" to use in the multiplication? Like this:

1 | signal data : std_logic_vector(13 downto 0); |

2 | signal data_unsigned : unsigned(13 downto 0); |

3 | |

4 | data_unsigned <= data_unsigned * unsigned(integer(1.5*8192.0),data'length))... |

5 | |

6 | data <= std_logic_vector(data_unsigned); |

I'm a little bit lost with all these types...

sebgimi wrote: > I'm a little bit lost with all these types... Have a look there (try Google translator,its German): http://www.lothar-miller.de/s9y/categories/16-Numeric_Std And then remind: in the numeric_std the multiplication is only defined for signed and unsigned vectors. Then your calculation must look this way

1 | data <= std_logic_vector( signed(data) * to_signed(integer(1.5*8192.0),data'length) ); |

But why not definig data itself as a signed vector? The result of a vector multiplication is twice the with of a single vector (or the sum of the bits of both). I would do the calculation in integer. Then you don't have to hassle aruond with vector lengths:

1 | data <= std_logic_vector(to_signed(to_integer(signed(data)) * integer(1.5*8192.0), data'length)); |

Lothar Miller wrote: > But why not definig data itself as a signed vector? > The result of a vector multiplication is twice the with of a single > vector (or the sum of the bits of both). > > I would do the calculation in integer. Then you don't have to hassle > aruond with vector lengths: data <= > std_logic_vector(to_signed(to_integer(signed(data)) * > integer(1.5*8192.0), data'length)); So, if I understand right, I have to declare data as a signed vector of 28 bits and write the line of calculation above ?

sebgimi wrote: > declare data as a signed vector of 28 bits and write the line of > calculation above ? It you do so, this will be enough: data <= to_signed(to_integer(data) * integer(1.5*8192.0), data'length);