I have a problem with this question. I need these project and I will use just the main file. Is there anybody who will help me ? Thanks ? Question: main file in which you use 2 4-bit-adder modules to make an 8-bit adder
Show what you have done and point out the problem with it. Then maybe one will help you with your homework. At least we could see, which HDL you address...
I have these 2 4-bit's adder module. How can I combined and merged these in main file for obtain 8-bit adder ?
CCC CCC wrote: > I have these 2 4-bit's adder module. Whats the difference between them? As far as I can see both of those modules are similar 1 bit full adders. So you must chain up 8 of them to get the desired 8 bit adder.
Is this code even compiling without declaring S and Cout as "reg"? Anyhow at best, these are one bit full adders, as already mentioned by Lothar.
How can I obtain 8Bit full adder from 2 4-bit full adder ?
I found this code for 4-bit full adder and I tried to combined them but
i didn't do this.
module fullAdder(
input a,
input b,
input cin,
output s,
output cout );
assign {cout,s} = a + b + cin;
endmodule
Could you help me how can I obtain this ?
how to connect instantiated modules by name: http://www.asic-world.com/verilog/syntax2.html e.g a two bit adder:
1 | module adder_2bit( |
2 | input [1:0] abus, |
3 | input [1:0] bbus, |
4 | input cin, |
5 | output [1:0] sumbus, |
6 | output cout ); |
7 | |
8 | wire ctemp1; |
9 | |
10 | fullAdder u0 ( |
11 | .a(abus[0]) , |
12 | .b(bbus[0]) , |
13 | .cin(ci) , |
14 | .sum(sumbus[0]) , |
15 | .cout(ctemp1) |
16 | ); |
17 | fullAdder u1 ( |
18 | .a(abus[1]) , |
19 | .b(bbus[1]) , |
20 | .cin(ctemp1) , |
21 | .sum(sumbus[1]) , |
22 | .cout(cout) |
23 | ); |
24 | endmodule |
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