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is it possible to select what kind of adder will be used in megawizard plug in, for example,, i want all of addition will be ripple carry.
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there is no ripple carry adder. this is just theory from the human view.
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we're doing a research about comparative analysis of various edge detection, one of the parameters is the speed, so the panel suggest that we need to be specific of what architecture we will use in multiplier, adder, etc. to make it fair with other algorithm.
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From the Megawizzard, I think this is not possible. The Adder will either be implemented using dedicated hardware (DSP block adder) or using standard logic array blocks to match the described behaviour. Usually, as long as you get the required speed you don't care about how it's actually implemented. Maybe you'll find out how the DSP block adder(s) are implemented if you dig deep enough (for sure, it is not a ripple carry adder). However, if you want a ripple carry adder, you have to describe/build it by yourself with an entity forcing it to do so.
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Mark Jomari wrote: > we're doing a research about comparative analysis of various edge > detection, one of the parameters is the speed, so the panel suggest that > we need to be specific of what architecture we will use in multiplier, > adder, etc. to make it fair with other algorithm. An other way would be to opimize all the algorithms to max. speed, deciding for every mathematical unit which architecture will give the fastest result and compare in the end the transistor count (ASIC) or the number of used resources (FPGA). Keep in mind that the best algorithm for ASICs could be a different one than the best for FPGAs.
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we try to implement these algorithms, sobel, prewitt, robert, canny, laplacian of gaussian,. is it possible to program edge detection without using this megawizard???
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Mark Jomari wrote: > is it possible to program edge detection > without using this megawizard? Yes of course. Just use plain VHDL or verilog... Duke
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@ duke? sir , are you sure? how about the timing ? is it become a problem ?
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Mark Jomari wrote: > is it become a problem Not if you define properly your timing constraints. (*.sdc file...)