assign generic value to an output vhdl

guy Guest #3703117
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Hi everyone,

I'm a newbie in vhdl and I would like to know if is it possible to 
assign a generic value to an output in vhdl.

For instance:
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entity xxx is

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    generic(value : real);

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    port (a : in real;

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          b : in real;

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          s : out real);

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end xxx;

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archi archi of xxx is

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begin

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      s <= value;

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end archi;


If it is not can you help me to find an other way please ?
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Bitflüsterer Guest #3703174
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guy wrote:
> Ahah, what is the way to do what I want? I tried as I have wrote it
> above but in simulation I have not the good value.

As Lothar already wrote: Your code is sufficient to do what you want. If 
there is still a problem, please show the context (i.e. the testbench) 
and tell us in detail how and by what means you came to the conclusion, 
that the result is not what you expect.
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