Hi everyone, I'm a newbie in vhdl and I would like to know if is it possible to assign a generic value to an output in vhdl. For instance:
1 | entity xxx is |
2 | |
3 | generic(value : real); |
4 | |
5 | port (a : in real; |
6 | b : in real; |
7 | s : out real); |
8 | |
9 | end xxx; |
10 | |
11 | archi archi of xxx is |
12 | begin
|
13 | |
14 | s <= value; |
15 | |
16 | end archi; |
If it is not can you help me to find an other way please ?