Hi every one,
I'm writing a code for a dac in vhdl and I have some troubles during
simulation: a delay appears on two signals what is not what I want...
My code:
1 | library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 |
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5 | entity dac is
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6 |
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7 | generic (data_width : integer;
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8 | SDI_width : integer;
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9 | REF : real);
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10 |
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11 | port( SDI : in std_logic_vector (SDI_width - 1 downto 0);
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12 | SDO : out std_logic_vector(SDI_width - 1 downto 0);
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13 | SCK : in std_logic;
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14 | CLR : in std_logic; -- low level active
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15 | CS_LD : in std_logic; -- '0': CS / '1': LD
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16 | LDAC : in std_logic; -- low level active
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17 | Vout : out real
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18 | );
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19 |
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20 | end dac;
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21 |
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22 | architecture archi of dac is
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23 |
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24 | signal data : std_logic_vector(11 downto 0);
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25 | signal data_real : real;
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26 |
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27 | begin
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28 |
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29 | data <= SDI(15) & SDI(14) & SDI(13) & SDI(12) & SDI(11) & SDI(10) &
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30 | SDI(9) & SDI(8) & SDI(7) & SDI(6) & SDI(5) & SDI(4);
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31 |
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32 | P1: process(SCK)
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33 | begin
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34 |
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35 | data_real <= (real(to_integer(signed(data))));
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36 |
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37 | if (CLR = '0' or CS_LD = '0') then
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38 |
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39 | Vout <= 0.0;
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40 |
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41 | elsif (SCK'event and SCK = '1') then
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42 |
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43 | Vout <= data_real/(2.0**data_width) * REF;
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44 |
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45 | end if;
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46 |
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47 | end process;
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48 |
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49 |
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50 | end archi;
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In simulation this is a delay of 5 ns on the "data_real" signal and 15
ns on the signal "Vout".
Do you know what is wrong in my code and how to fix it please ?