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Forum: FPGA, VHDL & Verilog delay not wanted vhdl


von angelo (Guest)


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Hi every one,

I'm writing a code for a dac in vhdl and I have some troubles during 
simulation: a delay appears on two signals what is not what I want...

My code:
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dac is
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  generic (data_width : integer;
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     SDI_width  : integer;
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     REF        : real);
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  port(  SDI   : in  std_logic_vector (SDI_width - 1 downto 0);
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    SDO   : out std_logic_vector(SDI_width - 1 downto 0);
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    SCK   : in  std_logic;
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    CLR   : in  std_logic;  -- low level active
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    CS_LD : in  std_logic;   -- '0': CS / '1': LD
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    LDAC  : in  std_logic;  -- low level active
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    Vout  : out real
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      );
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end dac;
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architecture archi of dac is  
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signal data      : std_logic_vector(11 downto 0);
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signal data_real : real;
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begin
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  data <= SDI(15) & SDI(14) & SDI(13) & SDI(12) & SDI(11) & SDI(10) &
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    SDI(9) & SDI(8) & SDI(7) & SDI(6) & SDI(5) & SDI(4);    
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  P1: process(SCK)
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  begin
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    data_real <= (real(to_integer(signed(data))));
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    if (CLR = '0' or CS_LD = '0') then
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      Vout <= 0.0;
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    elsif (SCK'event and SCK = '1') then
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      Vout <= data_real/(2.0**data_width) * REF;
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    end if;
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  end process;
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end archi;

In simulation this is a delay of 5 ns on the "data_real" signal and 15 
ns on the signal "Vout".

Do you know what is wrong in my code and how to fix it please ?

von Lothar M. (lkmiller) (Moderator)


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angelo wrote:
> In simulation this is a delay of 5 ns on the "data_real" signal and 15
> ns on the signal "Vout".
Your problem ist the wrong sensitivity list...

Try this and think about it:
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  P1: process(SCK,data,CLR,CS_LD) ...

THis line can be shortened:
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data <= SDI(15) & SDI(14) & SDI(13) & SDI(12) & SDI(11) & SDI(10) &
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    SDI(9) & SDI(8) & SDI(7) & SDI(6) & SDI(5) & SDI(4);
Try it this way:
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data <= SDI(15 downto 4);

: Edited by Moderator
von angelo (Guest)


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Hi,

Thank you for your answer, with all your advices the issue is 
fixed...partially.

No more delay on data_real signal, but still on Vout signal. Now it's a 
5 ns delay instead 15 ns.

Did I miss something ?

von angelo (Guest)


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Never mind, I'm just silly!

It's all good! Cheers

von Lothar M. (lkmiller) (Moderator)


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angelo wrote:
> It's all good!
To all the others: there must be a "delay" due to the clock, obviously.

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