Hi,
I'm using generate to create 32 dff's to work as a shift register,
that part works great.
The problem is, that i want to input data only on rising edge of the
clock,
but the actual insert takes place half clk after that.
Do i need to change the generate itself?
thx !
this is the component that activates the generate:
1 | begin
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2 |
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3 | dffx: for i in 1 to 31 generate
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4 |
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5 | lsb: if i=1 generate
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6 | dff1: dff24 port map
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7 | (clk,rst,data_in,fir_array((24*i-1) downto (i-1)*24));
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8 | end generate lsb;
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9 |
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10 | msb: if (i>1)and(i<=31) generate
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11 | dffs: dff24 port map
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12 | (clk,rst,fir_array((24*(i-1)-1) downto (i-2)*24),fir_array((24*i-1) downto (i-1)*24));
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13 | end generate msb;
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14 | end process;
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15 | end generate dffx;
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this is the component that the generate use:
1 | architecture beh of dff24 is
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2 |
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3 |
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4 | begin
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5 |
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6 | process (clk, rst)
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7 |
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8 | begin
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9 | if(rst = '0') then
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10 | q <= "000000000000000000000000" ;
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11 |
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12 | else if (rising_edge(clk)) then
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13 | q <= d;
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14 | end if;
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15 | end if;
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16 | end process;
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17 |
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18 | end beh;
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