tester wrote:
> but it does still not not..
How did you find that out? What do you expect? And what happens?
Pls attach the whole vhdl-file (with *.vhd or *.vhdl extension), so that
the libraries and the port definiton also can be seen...
tester wrote:
> First process is for syncronizing the signal with the clock, and the
> other one is the debounching.
> Are they incorrectly made
This is unnecessary because at this position data_out and oldbtn MUST be
equal:
1 | if (data_out XOR oldbtn) = "0000"
|
Think about that...
> Are they incorrectly made
A switch bounces in the milliseconds range. You are syncing way, way
faster (in the sub microseconds range). First step is to implement a
prescaler, so that you are in the correct time division...
> Are they incorrectly made
They are much too complicated. The first process can be written as a
concurrent description without ANY change in behaviour:
1 | data_out <= switch when rising_edge(clk);
|
Why digging around with code like this
1 | if (data_out XOR oldbtn) /= "0000" then
|
when VHDL is able to handle it much better readable this way:
1 | if (data_out /= oldbtn) then
|
BTW:
data_out is a fairly bad name for a sync'ed switch...
Debouncing is only the first step. Next will consequently be a
edge-detection. Have a look at this (try google translator, its German):
http://www.lothar-miller.de/s9y/categories/5-Entprellung