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Forum: FPGA, VHDL & Verilog std_logic_vector won't "keep" certain values


von Amir (Guest)


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I was asked to design a simple can dispensing machine using VHDL.
I have an input called CoinIn and is defined as an std_logic_vector(1 
downto 0);
for some reason, when I try to force it with a "11" it will treat it as 
a "01" and when i try to force it with a "10" it will treat it at "00".
Does anyone have any idea what the problem might be?

von Amir (Guest)


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Here's the code BTW (it's not 100% ready yet):
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library ieee;
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use ieee.std_logic_1164.all;
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ENTITY FSM IS
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PORT (CLK : in std_logic; --Clock, active high
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      RSTn : in std_logic; --Async. Reset, active low
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      CoinIn : in std_logic_vector (1 downto 0) ; --Which coin was inserted
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      Soda : out std_logic := '0'; --Is Soda dispensed ?
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      CoinOut : out std_logic_vector (1 downto 0) --Which coin is dispensed?
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  );
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END ENTITY;
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ARCHITECTURE behavior of FSM IS
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  TYPE state IS ( start, change, can, pending );
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  SIGNAL present_state, next_state : state;
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  SIGNAL Count : integer range 0 to 6:=0;
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BEGIN
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  PROCESS (RSTn, clk, CoinIn) --sync part
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  BEGIN
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    IF RSTn ='0' THEN
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      present_state <= start;
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    ELSIF rising_edge(clk) THEN  
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      present_state <= next_state;
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    END IF;
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  END PROCESS;
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  PROCESS (CoinIn, clk, present_state, next_state) --combinational 
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  VARIABLE SodaVar : std_logic;
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  VARIABLE CoinOutVar : std_logic_vector(1 downto 0);
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  BEGIN
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    CoinOutVar := "00";
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    CASE present_state is
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      WHEN start =>
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        SodaVar := '0';
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        IF CoinIn = "01" then
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          next_state <= pending;
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          count <= 1;
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        ELSIF CoinIn = "10" then
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          next_state <= can;
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          count <= 0;
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        ELSIF CoinIn = "11" then
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          next_state <= change;
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          count <= 5;
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        ELSIF CoinIn = "00" THEN 
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          next_state <= start;
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          count <= 0;
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        END IF;
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      WHEN pending =>
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        SodaVar := '0';
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        IF CoinIn = "01" then
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          next_state <= can;
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          count <= 2;
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        ELSIF CoinIn = "10" then
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          next_state <= change;
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          count <= 3;
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        ELSIF CoinIn = "11" then
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          next_state <= change;
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          count <= 6;
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        ELSIF CoinIn = "00" then
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          next_state <= pending;
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        END IF;
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      WHEN change =>
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        SodaVar := '0';
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        IF ((count - 2) = 1) then 
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          CoinOutVar := "01";
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          count <= 0;
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          next_State <= can;
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        ELSIF ((count -2) = 0) then
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          next_state <= can;
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          count <= 0;
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          CoinOutVar := "00";
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        ELSE          
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          next_state <= change;
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          count <= count - 2;
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          CoinOutVar := "10";
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        END IF;
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      WHEN can =>
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        next_state <= start;
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        SodaVar := '1';
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        count <= 0;
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    END CASE;
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    Soda <= SodaVar;
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    CoinOut <= CoinOutVar;
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  END PROCESS;
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END ARCHITECTURE;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Amir wrote:
> Here's the code BTW
Please use the formatting tags (see screenshot).

> when I try to force it with a "11" it will treat it as a "01"
How do you see that?
How do you "force" it?
Don't you have a test bench for this vending machine?

: Edited by Moderator

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