I am having som problems with my code. I've written some code which changes the state when the switches i press matches the sequence i check it for.. The sequence is in an array, and for reason is the array very weird (for me to understand).. But for some reason , even when i press the correct sequence does it not enter the next state. I tried simulating it, and i haven't been able to see where i am Going wrong so this is my last chance to find out where i am going wrong. Please help..
John Mayer wrote: > I've written some code
if switch /= "0000" then
if switch = LISTEN(pointer+1) and (pointer-1) < top_pointer then
You MUST NOT use external asynchronous signals without synching them to the FPGAs clock with two flipflops. Otherwise you will experience strange and unexpected behaviour now and then... John Mayer wrote: > I tried simulating it, With what simulator? If it is ISIM its clear: > and i haven't been able to see where i am Going wrong You cannot trace variables with ISIM. > so this is my last chance to find out where i am going wrong. No, it isn't the last chance to let others do your work without saying WHAT you expect and WHAT you get. > even when i press the correct sequence What ist "the correct sequence"? Where can "the correct sequence" be found in your test bench? Why do you post the complete projekt when it would be enough to see the two questionable vhdl files? So my conclusion is: use signals instead of all those variables! You do not need those variables and without them you will not get in troubles with the behaviour of variables. And additionally you will be able to SEE and TRACE the signal in the simulator.
This is the sequence Constant LISTEN: LIST := ("1000","1000","1000","0100","0010","0001","1000","0100","0010","0001"); POinter starts at 0, and for each round is incremented. So the first sequence is "0001", and the next is "0010" and so on.
It removes all the warnings that appears during implementation, and generationg program file. But when i simulate it says that the signal are undefined.
Please mark the correct answer with a cross: [ ] I do not read the answers to my posts [ ] I do not understand the answers to my posts John Mayer wrote: > But when i simulate it says that the signal are undefined. Try this:
variable prescaler: integer range 0 to 50000000 := 0;
[x] I do not understand the answers to my (your) posts If you are referering to the fact that i should use signal instead of variables, then yes. I've changed them all to be signal, and ISim is still defining them as beeing undefined.
: Edited by User
John Mayer wrote: > I've changed them all to be signal And how does the code look like now? So pls. attach your two relevant vhdl files (the game and the test bench) and a screenshot of the simulation...
: Edited by Moderator