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Forum: FPGA, VHDL & Verilog discard zero values in vhdl


von enao (Guest)


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hi all

if i have vhdl code and the output such as std_logic_vector(7 downto 0) 
and the output (254,0,0,0,0,0,0,300,0,0,0,0,450,0,0,0,0,0,0,0.. etc and 
i want to get ride of such zero
values and get only (254,300,450.....) i.e discard any zero output and 
get non zero output. how can i do that in vhdl cod??

thanks for any help.

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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enao wrote:
> i have vhdl code
Show it.
Where do the values come from? How are they generated? Are the values 
synchronous to a clock?

von enao (Guest)


Attached files:

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Lothar Miller wrote:

> Show it.
it is the code
1
library ieee;
2
    use ieee.std_logic_1164.all;
3
    use IEEE.numeric_std.all;
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    entity bubblesort is
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    port(
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        clk      : in std_logic;
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        we       : in std_logic := '1';
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        trigraph : in std_logic_vector(7 downto 0) := x"0F";
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        duration : in integer range 0 to 1023 := 5;
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        read     : in std_logic := '0';
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        dout     : out std_logic_vector(7 downto 0)
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    );
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    end entity;
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    architecture rtl of bubblesort is
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    signal address, rd_addr : integer range 0 to 1023 := 0;
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    signal trigraph_d : std_logic_vector(7 downto 0);
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    signal we_d : std_logic := '0';
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    type mem is array(0 to 1023) of std_logic_vector(7 downto 0);
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    signal ram : mem := ((others=> (others=>'0')));
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    begin
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    --infer ram
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    process(clk)
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    begin
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    if(rising_edge(clk)) then
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       dout <= ram(address);
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       if(we_d = '1') then
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          ram(address) <= trigraph_d;
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       end if;
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    end if;
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    end process;
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    process(clk)
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    begin
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    if rising_edge(clk) then
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      we_d <= we;
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      trigraph_d <= trigraph;
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      if read = '1' then
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        if rd_addr < 1023 then
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          rd_addr <= rd_addr + 1;
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        end if;
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      end if;
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      if read = '0' then
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        address <= duration;
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      else
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        address <= rd_addr;
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      end if;
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    end if;
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    end process;
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    end rtl;

> Where do the values come from? How are they generated?
the values are dout it generated from comparing every value to address 
if it is equal output trigraph

> Are the values synchronous to a clock?
yes it is synchronous

von Duke Scarring (Guest)


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enao wrote:
> i.e discard any zero output and
> get non zero output.
Just make a copy of your values, but only if they match your criteria.

Duke

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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I cannot find any reason for NOT showing the zeros. But this add-on 
would show a non-zero value throughout:
1
    signal dout_buf : std_logic_vector(7 downto 0) := x"ff";
2
3
    :
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    process(clk)
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    begin
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    if(rising_edge(clk)) then
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       if ram(address)!=x"00" then
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          dout_buf <= ram(address);
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       end if;
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       :
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    end if;
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    end process;
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    dout <= dout_buf;
But usually it is better to output an additional valid signal together 
with the data to show an external component: "Now this value is ready to 
be used!"

von ENAO (Guest)


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i try to do it with that
1
library ieee;
2
    use ieee.std_logic_1164.all;
3
    use IEEE.numeric_std.all;
4
5
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    entity bubblesort is
7
    port(
8
        clk           : in std_logic;
9
        we            : in std_logic;
10
        trigraph_in   : in std_logic_vector(7 downto 0);
11
        duration_in   : in integer range 0 to 1023;
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        read          : in std_logic;
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        trigraph_out  : out std_logic_vector(7 downto 0);
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        duration_out  : out integer range 0 to 1023
16
        
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    );
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    end entity;
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    architecture rtl of bubblesort is
21
      
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    signal addr, rd_addr, addr_d : integer range 0 to 1023 := 0;
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    signal trigraph_d : std_logic_vector(7 downto 0);
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    signal we_d : std_logic := '0';
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    type mem is array(0 to 1023) of std_logic_vector(7 downto 0);
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    signal ram : mem := ((others=> (others=>'0')));
28
    
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    signal ram_out : std_logic_vector(7 downto 0);
30
    
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    begin
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    --infer ram
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    process(clk)
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    begin
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    if(rising_edge(clk)) then
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       ram_out <= ram(addr);
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       if(we_d = '1') then
40
          ram(addr) <= trigraph_d;
41
       end if;
42
    end if;
43
    end process;
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    process(clk)
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    begin
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    if rising_edge(clk) then
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      we_d <= we;
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      trigraph_d <= trigraph_in;
51
           
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      if read = '1' then
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        if rd_addr < 1023 then
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          rd_addr <= rd_addr + 1;
55
        end if;
56
      end if;
57
      
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      if read = '0' then
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        addr <= duration_in;
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      else
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        addr <= rd_addr;
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      end if;
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      addr_d <= addr;
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      if ram_out /= x"00" then
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        duration_out <= addr_d;
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        trigraph_out <= ram_out;
68
      end if;
69
      
70
    end if;
71
    end process;
72
73
          
74
    end rtl;

but i want to know how to remove breaks in regular stream ecause i want 
to sum them.

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