EmbDev.net

Forum: FPGA, VHDL & Verilog discard zero values in vhdl


Author: enao (Guest)
Posted on:

Rate this post
0 useful
not useful
hi all

if i have vhdl code and the output such as std_logic_vector(7 downto 0) 
and the output (254,0,0,0,0,0,0,300,0,0,0,0,450,0,0,0,0,0,0,0.. etc and 
i want to get ride of such zero
values and get only (254,300,450.....) i.e discard any zero output and 
get non zero output. how can i do that in vhdl cod??

thanks for any help.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
enao wrote:
> i have vhdl code
Show it.
Where do the values come from? How are they generated? Are the values 
synchronous to a clock?

Author: enao (Guest)
Posted on:
Attached files:
  • preview image for 1.jpg
    1.jpg
    287 KB, 106 downloads
  • preview image for 2.jpg
    2.jpg
    280 KB, 97 downloads
  • preview image for 3.jpg
    3.jpg
    281 KB, 85 downloads
  • preview image for 4.jpg
    4.jpg
    280 KB, 94 downloads
  • preview image for 5.jpg
    5.jpg
    280 KB, 92 downloads

Rate this post
0 useful
not useful
Lothar Miller wrote:

> Show it.
it is the code
library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.numeric_std.all;


    entity bubblesort is
    port(
        clk      : in std_logic;
        we       : in std_logic := '1';
        trigraph : in std_logic_vector(7 downto 0) := x"0F";
        duration : in integer range 0 to 1023 := 5;
        read     : in std_logic := '0';
        dout     : out std_logic_vector(7 downto 0)
    );
    end entity;

    architecture rtl of bubblesort is
      
    signal address, rd_addr : integer range 0 to 1023 := 0;
    signal trigraph_d : std_logic_vector(7 downto 0);
    signal we_d : std_logic := '0';

    type mem is array(0 to 1023) of std_logic_vector(7 downto 0);
    signal ram : mem := ((others=> (others=>'0')));

    begin

    --infer ram
    process(clk)
    begin
    if(rising_edge(clk)) then
       dout <= ram(address);
       if(we_d = '1') then
          ram(address) <= trigraph_d;
       end if;
    end if;
    end process;

    process(clk)
    begin
    if rising_edge(clk) then
      
      we_d <= we;
      trigraph_d <= trigraph;
      
      if read = '1' then
        if rd_addr < 1023 then
          rd_addr <= rd_addr + 1;
        end if;
      end if;
      
      if read = '0' then
        address <= duration;
      else
        address <= rd_addr;
      end if;
      
    end if;
    end process;

    end rtl;

> Where do the values come from? How are they generated?
the values are dout it generated from comparing every value to address 
if it is equal output trigraph

> Are the values synchronous to a clock?
yes it is synchronous

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
enao wrote:
> i.e discard any zero output and
> get non zero output.
Just make a copy of your values, but only if they match your criteria.

Duke

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
I cannot find any reason for NOT showing the zeros. But this add-on 
would show a non-zero value throughout:
    signal dout_buf : std_logic_vector(7 downto 0) := x"ff";

    :

    process(clk)
    begin
    if(rising_edge(clk)) then
       if ram(address)!=x"00" then
          dout_buf <= ram(address);
       end if;
       :
    end if;
    end process;

    dout <= dout_buf;
But usually it is better to output an additional valid signal together 
with the data to show an external component: "Now this value is ready to 
be used!"

Author: ENAO (Guest)
Posted on:

Rate this post
0 useful
not useful
i try to do it with that
library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.numeric_std.all;


    entity bubblesort is
    port(
        clk           : in std_logic;
        we            : in std_logic;
        trigraph_in   : in std_logic_vector(7 downto 0);
        duration_in   : in integer range 0 to 1023;
        read          : in std_logic;
                
        trigraph_out  : out std_logic_vector(7 downto 0);
        duration_out  : out integer range 0 to 1023
        
    );
    end entity;

    architecture rtl of bubblesort is
      
    signal addr, rd_addr, addr_d : integer range 0 to 1023 := 0;
    signal trigraph_d : std_logic_vector(7 downto 0);
    signal we_d : std_logic := '0';

    type mem is array(0 to 1023) of std_logic_vector(7 downto 0);
    signal ram : mem := ((others=> (others=>'0')));
    
    signal ram_out : std_logic_vector(7 downto 0);
    

    begin

    --infer ram
    process(clk)
    begin
    if(rising_edge(clk)) then
       ram_out <= ram(addr);
       if(we_d = '1') then
          ram(addr) <= trigraph_d;
       end if;
    end if;
    end process;

    process(clk)
    begin
    if rising_edge(clk) then
      
      we_d <= we;
      trigraph_d <= trigraph_in;
           
      if read = '1' then
        if rd_addr < 1023 then
          rd_addr <= rd_addr + 1;
        end if;
      end if;
      
      if read = '0' then
        addr <= duration_in;
      else
        addr <= rd_addr;
      end if;
      
      addr_d <= addr;
      if ram_out /= x"00" then
        duration_out <= addr_d;
        trigraph_out <= ram_out;
      end if;
      
    end if;
    end process;

          
    end rtl;

but i want to know how to remove breaks in regular stream ecause i want 
to sum them.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.