Hi, I have a group of incoming signals with different bit width belonging to single transaction. I have to store all these inside FIFO or buffer and forward all these to different block.I am coding in verilog. Is there any way to do this without creating individual queue for each signal. Do verilog has something similar to structure in C so my problem can be solved?? Thanks in advance..
Guruprasad Hegde wrote: > Do verilog has something similar to structure in C so my problem can > be solved?? > No, verilog doesn't have structures. You can switch to SystemVerilog, but you have to ensure your toolchain supports it. Altenativly use VHDL.