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Forum: FPGA, VHDL & Verilog Mutiple source drivers - How to resolve it??


von John M. (215)


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I have this process
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state_fail_win <= test;
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process(clk,anode,counter_1,counter_10, state_fail_win,anode,counter_1r,counter_10r)
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variable prescaler: integer range 0 to 49999999 := 0;
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begin
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if rising_edge(clk) then
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    if(prescaler < 49999999/200) then   
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    prescaler := prescaler + 1;    
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    else
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      prescaler := 0;
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      anode <= anode + '1';
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    end if;
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end if;    
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if state_fail_win = '1' then 
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  if (counter_1 < 9) then        
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    counter_1 <= counter_1 + 1;
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  else
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    counter_1 <= 0;
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      if (counter_10 < 9) then        
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        counter_10 <= counter_10 + 1;  
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      else 
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        counter_10 <= 0;
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        counter_1 <= 0;
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      end if;
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  end if;
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end if;
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state_fail_win <= '0';
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  if state_fail_win = '0' then
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    case anode is
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      when "00" => SEG <= counter_1r; 
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      when "01" => SEG <= counter_10r;
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      when "10" => SEG <= d;
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      when "11" => SEG <= r;    
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      when others => SEG <= "00000000";
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    end case;
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  end if;
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end process;
I don't quite see how i get this error message..
Multi-source in Unit <segment> on signal <test>; this signal is 
connected to multiple drivers.
But how can i Resolve it??

: Edited by User
von Duke Scarring (Guest)


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John Mayer wrote:
> process(clk,anode,counter_1,counter_10,
> state_fail_win,anode,counter_1r,counter_10r)
> variable prescaler: integer range 0 to 49999999 := 0;
> begin
> if rising_edge(clk) then
>     if(prescaler < 49999999/200) then
>     prescaler := prescaler + 1;
>     else
>       prescaler := 0;
>       anode <= anode + '1';
>     end if;
Uhh.
1. You mix up sequential (clk) and combinatorical (without clk) logic in 
the same process. That's very advanced and usally confusing for 
beginners.

2. At least the signal state_fail_win is driven on diffrent places: 
Outside the process and inside the process. That's construct cannot map 
to hardware.

Remember this: Drive a signal only at one point and read it wherever 
you need it. A process is like a chip in your circuit with inputs and 
outputs.

Duke

von FPGA-advisor (Guest)


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you should learn to describe any of the signals in a design only in one 
process rather than accesing it from various places.

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