John Mayer wrote:
> process(clk,anode,counter_1,counter_10,
> state_fail_win,anode,counter_1r,counter_10r)
> variable prescaler: integer range 0 to 49999999 := 0;
> begin
> if rising_edge(clk) then
> if(prescaler < 49999999/200) then
> prescaler := prescaler + 1;
> else
> prescaler := 0;
> anode <= anode + '1';
> end if;
Uhh.
1. You mix up sequential (clk) and combinatorical (without clk) logic in
the same process. That's very advanced and usally confusing for
beginners.
2. At least the signal state_fail_win is driven on diffrent places:
Outside the process and inside the process. That's construct cannot map
to hardware.
Remember this: Drive a signal only at one point and read it wherever
you need it. A process is like a chip in your circuit with inputs and
outputs.
Duke