Mutiple source drivers - How to resolve it??

John M. (215) OP 2014-05-02 08:53 #3639487

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I have this process

state_fail_win <= test;
process(clk,anode,counter_1,counter_10, state_fail_win,anode,counter_1r,counter_10r)
variable prescaler: integer range 0 to 49999999 := 0;
if rising_edge(clk) then
    if(prescaler < 49999999/200) then   
    prescaler := prescaler + 1;    
      prescaler := 0;
      anode <= anode + '1';
    end if;
end if;    
if state_fail_win = '1' then 
  if (counter_1 < 9) then        
    counter_1 <= counter_1 + 1;
    counter_1 <= 0;
      if (counter_10 < 9) then        
        counter_10 <= counter_10 + 1;  
      else 
        counter_10 <= 0;
        counter_1 <= 0;
      end if;
  end if;
state_fail_win <= '0';
  if state_fail_win = '0' then
    case anode is
      when "00" => SEG <= counter_1r; 
      when "01" => SEG <= counter_10r;
      when "10" => SEG <= d;
      when "11" => SEG <= r;    
      when others => SEG <= "00000000";
    end case;
  end if;
end process;

I don't quite see how i get this error message..
Multi-source in Unit <segment> on signal <test>; this signal is 
connected to multiple drivers.
But how can i Resolve it??

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Duke Scarring Guest 2014-05-02 10:19 #3639559

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John Mayer wrote:
> process(clk,anode,counter_1,counter_10,
> state_fail_win,anode,counter_1r,counter_10r)
> variable prescaler: integer range 0 to 49999999 := 0;
> begin
> if rising_edge(clk) then
>     if(prescaler < 49999999/200) then
>     prescaler := prescaler + 1;
>     else
>       prescaler := 0;
>       anode <= anode + '1';
>     end if;
Uhh.
1. You mix up sequential (clk) and combinatorical (without clk) logic in 
the same process. That's very advanced and usally confusing for 
beginners.

2. At least the signal state_fail_win is driven on diffrent places: 
Outside the process and inside the process. That's construct cannot map 
to hardware.

Remember this: Drive a signal only at one point and read it wherever 
you need it. A process is like a chip in your circuit with inputs and 
outputs.

Duke

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FPGA-advisor Guest 2014-05-02 11:44 #3639656

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you should learn to describe any of the signals in a design only in one 
process rather than accesing it from various places.

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