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Forum: FPGA, VHDL & Verilog delay for syntezing on FPGA?

von John M. (215)

2014-04-30 21:24

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I have this problem with my VHDL code.

if pointer <= (top_pointer) and test = '0' then
       LED <= LISTEN(pointer);
       pointer := pointer + 1;
end if;

The Idea with this piece of code is that as i've tried to state is as 
long pointer is less than top pointer, LED has to display what inside 
the array listen and then increment the pointer.

the problem is that it isn't showing what the array contain.

My theory I am missing a prescaler, so i tried adding one,

if pointer <= (top_pointer) and test = '0' then
  if(prescaler < 49999999/1) then
    prescaler := prescaler + 1;
  else
    prescaler := 0;
LED <= LISTEN(pointer)
pointer := pointer + 1;
  end if;
end if;

but still same result..What am I doing wrong here??

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Re: delay for syntezing on FPGA?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2014-04-30 23:00

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You do not attach the questionable VHDL code. So no one is able to see 
the definition of the types...

Why do you open a new thread for an old question?

John Mayer wrote:
> My theory I am missing a prescaler, so i tried adding one,
Did you read and try to understand my recent answers?
Is there any clock in your design?

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Re: delay for syntezing on FPGA?

von John M. (215)

2014-04-30 23:01

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My code is attached in my old thread.
Yes there  is a clock attached in my design??

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Re: delay for syntezing on FPGA?

von Lothar M. (Company: Titel) (lkmiller) (Moderator)

2014-05-01 00:05

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John Mayer wrote:
> My code is attached in my old thread.
It isn't attached, you only added a link to some external site.
> my old thread.
For all the others:
http://embdev.net/topic/332350

> Yes there  is a clock attached in my design??
It is, but up to now I did what I said: not reading an external link to 
your code.

John Mayer wrote:
> the problem is that it isn't showing what the array contain.
What does it show instead? And how did you find that out? Did you 
simulate your design? What do you exptect to happen?


BTW:
You are playing a high league with this here:
shared variable top_pointer: integer range 0 to 4 := 0;
I rarely need a shared variable. And if so it is only for simulation. 
Can your synthesizer handle shared variables?