Why is this incorrect??

OP #3636937
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I don't get why this is incorrect???

i am trying to make hierachical design, but i am getting som weird 
errors.
this is my code.
1
entity top is
2
    Port ( CLock : in  STD_LOGIC;
3
           LED : out STD_LOGIC_vector(3 downto 0);
4
           Switch : in  STD_LOGIC);
5
end top;
6
architecture Behavioral of top is
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Signal numBER: std_logic_vector (1 downto 0);
8

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component randomnumber 
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port (
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  clk : in std_logic;
12
  gameon: in std_logic;
13
  bitteD: out std_logic_vector (1 downto 0)
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      );
15
end component;
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component randtosequence
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Port (
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  LED1 : out  STD_LOGIC_VECTOR (3 downto 0);
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  randbit : in  STD_LOGIC_VECTOR (1 downto 0)
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    );
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end component;
22

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begin
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randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bitted => number); 
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rantosequence1: randtosequence port map(randbit <= number);
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LED <= LED1;
27
end Behavioral;

I am getting these error which i don't understand.

ERROR:HDLParsers:3312 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. 
Undefined symbol 'randbit'.
ERROR:HDLParsers:1209 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. 
randbit: Undefined symbol (last report in this block)
ERROR:HDLParsers:3324 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. IN 
mode Formal randbit of randtosequence with no default value must be 
associated with an actual value.
ERROR:HDLParsers:3312 - "C:/.Xilinx/randomnumber/top.vhd" Line 57. 
Undefined symbol 'LED1'.
ERROR:HDLParsers:1209 - "C:/.Xilinx/randomnumber/top.vhd" Line 57. LED1: 
Undefined symbol (last report in this block)

I don't understand why they are undefined, haven't i defined them??
Moderator (Company: Titel) #3637041
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John Mayer wrote:
> Could you specifiy where the missing ) is???
Of course, but to give you a little bit of a learning effect you will 
have to find this yourself. Two little hints:
1. It is somewhere in the lines 56 and 57.
2. How many ports has randtosequence? How many did you connect?

> Isnt a => B , saying that B has the value of a
> and a <= B says that a has the value of B
> or am I wrong?
Yes, you are. In no VHDL literature you will find that definition. And 
in a port list there only one of the two arrows allowed.
OP #3637097
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Ok.. i correct my mistakes, i've generated the program file, but nothing 
appears to happen on the board.
1
entity top is
2
    Port ( CLock : in  STD_LOGIC;
3
           LED : out STD_LOGIC_vector(3 downto 0);
4
           Switch : in  STD_LOGIC
5
       );
6
end top;
7
architecture Behavioral of top is
8
Signal nummer: std_logic_vector (1 downto 0);
9

10
component randomnumber 
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port (
12
      clk : in std_logic;
13
      gameon: in std_logic;
14
      bittet: out std_logic_vector (1 downto 0)
15
    );
16
end component;
17
component randtosequence
18
Port (
19
        LED1 : out  STD_LOGIC_VECTOR (3 downto 0);
20
        randbit : in  STD_LOGIC_VECTOR (1 downto 0)
21
    );
22
end component;
23

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begin
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randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bittet => nummer); 
26
rantosequence1: randtosequence port map(LED1 => LED, randbit => nummer);
27
end Behavioral;

I've tested each module individually, and the work.
So something must be wrong on how I've connected it.

Gameon is just (on/off switch for the game)
bittet is generate psuedo random number (std_logic_vector(1 downto 0)) 
using a LFSR.
LED1 is just the LED on the board.
randbit interprets the bittet, and convert to sequence which the LED 
displays...
Moderator (Company: Titel) #3637414
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There are some mismatches!
These are four pins:
> LED : out STD_LOGIC_vector(3 downto 0);
This is one pin:
> NET "LED" LOC = "J14"
And there is no gameon in the port of your top level entity:
> NET "gameon" LOC = "G18";

Pls post your VHDL file(s) and your UCF file for having a look at it...

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