Why is this incorrect??

John M. OP #3636937
Rate this post
• ▲ useful
▼ not useful 
I don't get why this is incorrect???

i am trying to make hierachical design, but i am getting som weird 
errors.
this is my code.
1
entity top is

2
    Port ( CLock : in  STD_LOGIC;

3
           LED : out STD_LOGIC_vector(3 downto 0);

4
           Switch : in  STD_LOGIC);

5
end top;

6
architecture Behavioral of top is

7
Signal numBER: std_logic_vector (1 downto 0);

8


9
component randomnumber 

10
port (

11
  clk : in std_logic;

12
  gameon: in std_logic;

13
  bitteD: out std_logic_vector (1 downto 0)

14
      );

15
end component;

16
component randtosequence

17
Port (

18
  LED1 : out  STD_LOGIC_VECTOR (3 downto 0);

19
  randbit : in  STD_LOGIC_VECTOR (1 downto 0)

20
    );

21
end component;

22


23
begin

24
randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bitted => number); 

25
rantosequence1: randtosequence port map(randbit <= number);

26
LED <= LED1;

27
end Behavioral;


I am getting these error which i don't understand.

ERROR:HDLParsers:3312 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. 
Undefined symbol 'randbit'.
ERROR:HDLParsers:1209 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. 
randbit: Undefined symbol (last report in this block)
ERROR:HDLParsers:3324 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. IN 
mode Formal randbit of randtosequence with no default value must be 
associated with an actual value.
ERROR:HDLParsers:3312 - "C:/.Xilinx/randomnumber/top.vhd" Line 57. 
Undefined symbol 'LED1'.
ERROR:HDLParsers:1209 - "C:/.Xilinx/randomnumber/top.vhd" Line 57. LED1: 
Undefined symbol (last report in this block)

I don't understand why they are undefined, haven't i defined them??
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #3637041
Rate this post
• ▲ useful
▼ not useful 
John Mayer wrote:
> Could you specifiy where the missing ) is???
Of course, but to give you a little bit of a learning effect you will 
have to find this yourself. Two little hints:
1. It is somewhere in the lines 56 and 57.
2. How many ports has randtosequence? How many did you connect?

> Isnt a => B , saying that B has the value of a
> and a <= B says that a has the value of B
> or am I wrong?
Yes, you are. In no VHDL literature you will find that definition. And 
in a port list there only one of the two arrows allowed.
Reply Quote Edit Delete Report post
John M. OP #3637097
Rate this post
• ▲ useful
▼ not useful 
Ok.. i correct my mistakes, i've generated the program file, but nothing 
appears to happen on the board.

1
entity top is

2
    Port ( CLock : in  STD_LOGIC;

3
           LED : out STD_LOGIC_vector(3 downto 0);

4
           Switch : in  STD_LOGIC

5
       );

6
end top;

7
architecture Behavioral of top is

8
Signal nummer: std_logic_vector (1 downto 0);

9


10
component randomnumber 

11
port (

12
      clk : in std_logic;

13
      gameon: in std_logic;

14
      bittet: out std_logic_vector (1 downto 0)

15
    );

16
end component;

17
component randtosequence

18
Port (

19
        LED1 : out  STD_LOGIC_VECTOR (3 downto 0);

20
        randbit : in  STD_LOGIC_VECTOR (1 downto 0)

21
    );

22
end component;

23


24
begin

25
randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bittet => nummer); 

26
rantosequence1: randtosequence port map(LED1 => LED, randbit => nummer);

27
end Behavioral;


I've tested each module individually, and the work.
So something must be wrong on how I've connected it.

Gameon is just (on/off switch for the game)
bittet is generate psuedo random number (std_logic_vector(1 downto 0)) 
using a LFSR.
LED1 is just the LED on the board.
randbit interprets the bittet, and convert to sequence which the LED 
displays...
Reply Quote Edit Delete Report post
Lothar M. Moderator (Company: Titel) #3637414
Rate this post
• ▲ useful
▼ not useful 
There are some mismatches!
These are four pins:
> LED : out STD_LOGIC_vector(3 downto 0);
This is one pin:
> NET "LED" LOC = "J14"
And there is no gameon in the port of your top level entity:
> NET "gameon" LOC = "G18";

Pls post your VHDL file(s) and your UCF file for having a look at it...
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.