Hi all! I modelize the component LTC2255 in vhdl, it's a 14 bits adc which is working like this: data_out <= v_in after 5*Tclk+Tp In my situation the delay is 5*8ns+5.4ns = 45.4ns, so I write: D <= std_logic_vector(to_signed(integer(IN_ADC*8192.0),D'length)) after 45.4 ns; The simulation results only 'U' value on the data_out waveform. I tested with a smaller value, 10ns for instance and that is good. Do you know why and how I can fix this please ? Thank you
angelo wrote: > Do you know why and how I can fix this please? You could try the transport model:
1 | D <= transport std_logic_vector(to_signed(integer(IN_ADC*8192.0),D'length)) after 45.4 ns; |
Duke
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