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Forum: FPGA, VHDL & Verilog error with if generate


von bob (Guest)


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Hi all,

I got some errors when I try to compile the following code:
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library peb_lib;
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use peb_lib.all;
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entity adc_simu is
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  port(  CLK     : in  std_logic;
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    MODE    : in real;
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    OF_out  : out std_logic; -- OF pin
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    D       : out std_logic_vector(13 downto 0)
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      );
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end adc_simu;
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architecture archi of adc_simu is  
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component adc
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  generic (RefH, RefL: real;
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     VDD: real);
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  port(  Ain_pos : in real;
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    Ain_neg : in  real;
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    CLK     : in  std_logic;
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    MODE    : in real;
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    OF_out  : out std_logic; -- OF pin
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    D       : out std_logic_vector(13 downto 0)
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      );
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end component;
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component square_generator
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  generic(LOW  : real;
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    HIGH : real);
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  port(wave: out real);
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end component;
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component triangle_generator
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  generic(AMP: real;
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    OFFSET: real;
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    FREQ: real;
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    PHASE :real);
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  port(wave: out real);
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end component;
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component sinus_generator
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  generic(AMP    : real;
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    OFFSET : real;
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    FREQ   : real;
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    PHASE  : real);
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  port(sinus: out real);
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end component;
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component sawtooth_generator
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  generic(AMP: real;
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    OFFSET: real;
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    FREQ: real;
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    PHASE : real);
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  port(sawtooth: out real);
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end component;
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signal plus: real;
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signal moins: real;
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type waveform is (sinus, triangle, sawtooth, square);
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signal wave_type: waveform := sinus;
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begin
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  TRI:if wave_type = triangle generate
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              Vplus: triangle_generator 
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                     generic map (AMP => 1.0,
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                                  OFFSET => 1.5,
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                                  FREQ => 100000.0,
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                                  PHASE => 0.0)
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                     port map (plus);
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               Vmoins: triangle_generator
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                     generic map (AMP => 1.0,
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                                  OFFSET => 1.5,
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                                  FREQ => 100000.0,
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                                  PHASE => 180.0)
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                     port map (moins);
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  end generate TRI;
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  SQ:if wave_type = square generate
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               Vplus: square_generator
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                     generic map (LOW => 1.0,
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                                  HIGH => 0.000122)    
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                     port map (plus);
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               Vmoins: square_generator
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                      generic map (LOW => 0.000122,
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                                   HIGH => 0.000244)
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                     port map (moins);
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  end generate SQ;
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  SIN: if wave_type = sinus generate
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                Vplus: sinus_generator
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                      generic map (AMP => 1.0,
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                                   OFFSET => 1.5,
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                                   FREQ => 10000000.0,
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                                   PHASE => 0.0)
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                      port map (plus);
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                Vmoins: sinus_generator
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                      generic map (AMP => 1.0,
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                                   OFFSET => 1.5,
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                                   FREQ => 10000000.0,
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                                   PHASE => 180.0)                  
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                       port map (moins);
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  end generate SIN;
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  SAW: if wave_type = sawtooth generate
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                 Vplus: sawtooth_generator
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                      generic map (AMP => 3.3,
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                                   OFFSET => 1.65,
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                                   FREQ => 10000000.0,
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                                   PHASE => 0.0)
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                      port map (plus);
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                 Vmoins: sawtooth_generator
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                      generic map (AMP => 3.3,
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                                   OFFSET => 1.65,
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                                   FREQ => 10000000.0,
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                                   PHASE => 180.0)
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                      port map (moins);
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  end generate SAW;
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  CAN: adc generic map (RefH => 1.0, RefL => -1.0, VDD => 3.3)
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           port map (plus, moins, CLK, MODE, OF_out, D);
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end archi;

Errors are:

../RTL/adc_simu.vhdl:
        TRI:            if wave_type = triangle generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,92|18): illegal reference of a 
signal (WAVE_TYPE) during static elaboration [12.3].
        SQ:             if wave_type = square generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,102|17): illegal reference of 
a signal (WAVE_TYPE) during static elaboration [12.3].
        SIN:            if wave_type = sinus generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,112|18): illegal reference of 
a signal (WAVE_TYPE) during static elaboration [12.3].
        SAW:            if wave_type = sawtooth generate
                                   |
ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,122|18): illegal reference of 
a signal (WAVE_TYPE) during static elaboration [12.3].

Can you tell me what is wrong in my code please!

von ChristophZ (Guest)


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bob wrote:
> type waveform is (sinus, triangle, sawtooth, square);
>
> signal wave_type: waveform := sinus;

For the condition in your "if...generate" construct you have to use a 
generic or a constant, because both are static values when you are doing 
a synthesis or the simulator compiles your sources.

bob wrote:
> ncvhdl_p: *E,ILSGRD (../RTL/adc_simu.vhdl,122|18): illegal reference of
> a signal (WAVE_TYPE) during static elaboration [12.3].

Read: "You are giving me a signal to decide what I should do, but a 
signal is some thing dynamic and I have to do a static (permanent) 
decision."

von bob (Guest)


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Thanks for your answer!

So, if I understand right I have to remplace the type waveform by a 
integer or generic type in the condition?

von ChristophZ (Guest)


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bob wrote:
> So, if I understand right I have to remplace the type waveform by a
> integer or generic type in the condition?

No. You don't have to replace the type. You can use any type and all the 
types you created yourself.

bob wrote:
> signal wave_type: waveform := sinus;

You have to chance wave_type, you can't use a signal here. You have to 
use a generic (defined in the entity) or in this case simply replace the 
word "signal" with "constant".

von Lothar M. (lkmiller) (Moderator)


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bob wrote:
> So, if I understand right I have to remplace the type waveform by a
> integer or generic type in the condition?
You understood him wrong. I'm not sure if it works, but try this:
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constant wave_type: waveform := sinus;

Or try a generic (but then you will have to define a package with your 
data type and include that in your entity)...

von bob (Guest)


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Yeah I was wrong. Lothar you're right, I have tested your idea before 
your post and is giving me no error.

Thank you both of you!

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