Forum: FPGA, VHDL & Verilog VHDL: Comaprision of different multipliers using filter

von ssss (Guest)

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Can somebody explain the algorithm for analysing/testing different booth 
multipliers like add&shift, array multiplier, booth radix-2,4,8 
Their speed,power and area consumption and overall performance ??

I am done with the coding of all those multipliers but have a problem 
with testing them.

von Duke Scarring (Guest)

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ssss wrote:
> have a problem with testing them.
Take a couple of CMOS chips, build your multipliers and you can measure 
speed, number of gates and powerconsumtion with scope, calculator and 


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