case port map

bob Guest #3630374
Rate this post
• ▲ useful
▼ not useful 
Hi all!

I have an idea for a code I am writing but I don't know if it's 
possible. Let me explain:

I want to connect a component with an other in function of a signal.
A thing like this:

case wave_type is

       when sinus =>  V_pos: sinus_wave generic map();
                                        port map();

                      V_neg: sinus_wave generic map();
                                        port map();

       when square => V_pos: square_wave generic map();
                                         port map();

                      V_neg: square_wave generic map();
                                         port map();

      when ..........etc


I have tested that but a signal expression is expected instead of port 
map...

Do you know a solution to get what I want? Thank you
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
ChristophZ Guest #3630390
Rate this post
• ▲ useful
▼ not useful 
If you would like to change the component used in your code when your 
design is synthesized then you can achieve it with the "generate" 
statement.

If you would like to change the used component during runtime (when your 
hw is running) you need to instantiante all components and you need a 
multiplexer to select the desired output (for example with a case 
statement like in your code).
Reply Quote Edit Delete Report post
bob Guest #3630397
Rate this post
• ▲ useful
▼ not useful 
ChristophZ wrote:
> If you would like to change the component used in your code when
> your
> design is synthesized then you can achieve it with the "generate"
> statement.
>
> If you would like to change the used component during runtime (when your
> hw is running) you need to instantiante all components and you need a
> multiplexer to select the desired output (for example with a case
> statement like in your code).

It's for simulation only. Can you explain what you mean by "generate" 
statement please?
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.