Hi everyone,
I'm writing a code for a triangular wave generator in vhdl, and I have a
little issue. I want a signal with Vmax =3.3V and I never reach this
value, the max is 3.2999...
There is not a really big difference but may will be damaging for what I
want to simulate with this signal (14 bits ADC).
Do you have any hint to get exactly the 3.3 value, if is it possible?
Thank you!
My code is below:
1 | library ieee;
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2 | use ieee.std_logic_1164 .all;
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3 | use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 | use ieee.math_real.all;
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6 |
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7 | entity test is
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8 |
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9 | generic(AMP: real;
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10 | OFFSET: real;
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11 | FREQ: real);
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12 |
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13 | port(triangle: out real);
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14 |
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15 | end test;
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16 |
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17 | architecture archi of test is
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18 |
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19 | signal tmp : real := 0.0;
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20 |
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21 | begin
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22 |
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23 | P1:process
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24 |
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25 | constant delta : real := 1000.0e-12;
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26 | constant fin : time := 1000 ps;
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27 |
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28 | variable t : real := 0.0;
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29 | variable Vmax : real := AMP/2.0;
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30 |
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31 | begin
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32 |
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33 | loop
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34 |
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35 | t := t + delta;
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36 | tmp <= OFFSET+Vmax*(2.0/math_pi)*arcsin(sin(math_2_pi*FREQ*t));
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37 | wait for fin;
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38 |
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39 | end loop;
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40 |
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41 | wait;
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42 |
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43 | end process P1;
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44 |
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45 | triangle <= tmp;
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46 |
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47 | end archi;
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