Hi everyone,
I'm writing a code for a triangular wave generator in vhdl, and I have a
little issue. I want a signal with Vmax =3.3V and I never reach this
value, the max is 3.2999...
There is not a really big difference but may will be damaging for what I
want to simulate with this signal (14 bits ADC).
Do you have any hint to get exactly the 3.3 value, if is it possible?
Thank you!
My code is below:
1  library ieee;

2  use ieee.std_logic_1164 .all;

3  use ieee.std_logic_arith.all;

4  use ieee.std_logic_unsigned.all;

5  use ieee.math_real.all;

6  
7  entity test is

8  
9  generic(AMP: real;

10  OFFSET: real;

11  FREQ: real);

12 

13  port(triangle: out real);

14 

15  end test;

16  
17  architecture archi of test is

18  
19  signal tmp : real := 0.0;

20  
21  begin

22  
23  P1:process

24 

25  constant delta : real := 1000.0e12;

26  constant fin : time := 1000 ps;

27 

28  variable t : real := 0.0;

29  variable Vmax : real := AMP/2.0;

30 

31  begin

32 

33  loop

34 

35  t := t + delta;

36  tmp <= OFFSET+Vmax*(2.0/math_pi)*arcsin(sin(math_2_pi*FREQ*t));

37  wait for fin;

38 

39  end loop;

40 

41  wait;

42 

43  end process P1;

44 

45  triangle <= tmp;

46 

47  end archi;
