I'm having difficulties designing a circuit in Verilog that displays 
(using the 7 segmen display) a 13-digit number (2921007134140). The 
digits have to appear one followed by another with a frequency that 
allows the viewer to read them.

Just for the record, I am using a Nexys™2 Spartan-3E FPGA Board.

What I did so far:

module top_module(
input [3:0]number,
output [7:0]segment,
input [1:0]selection,
output [3:0]digit);

decoder decoder(.in(selection), .out(digit));

seven_segment_rom seven_segmen_rom(.addr(number), .data(segment));

module seven_segment_rom(
input [3:0]addr,
output reg [7:0]data);

always@(addr)
case(addr)
0:data=8'b01100000;
1:data=8'b11110011;
2:data=8'b11000100;
3:data=8'b11000001;
4:data=8'b01010011;
5:data=8'b01001001;
6:data=8'b01001000;
7:data=8'b11100011;
8:data=8'b01000000;
9:data=8'b01000001;
default data=8'b00001100;
endcase
endmodule

module decoder(input [1:0] in, output[3:0]out);
assign out=~(1<<in);
endmodule


The convention used is FPGABCDE/76543210

I have also designed a counter (for the frequency thing) but I'm not 
sure where it can fit in here and how to use it exactly.

I can post the constraints too, for better understanding if that is 
necessary.

Overall, I have no idea how to connect all these modules in Xilinx to 
obtain that digit-after-digit display of the number.