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Forum: FPGA, VHDL & Verilog Receiving UART


von Michelle N. (nojman)


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Hi!

I have a assignment to write a receiving part of a UART circuit. I have 
got this code but how can rewrite it so it's the receiving part?
I tried to take away all the "tx" rows (transmission) but then i could 
not get pas the test bench.

Would be really glad for any help.

The code.

1
library ieee;
2
    use ieee.std_logic_1164.all;
3
    use ieee.std_logic_unsigned.all;
4
5
entity uart is
6
    port (
7
        reset       :in  std_logic;
8
        txclk       :in  std_logic;
9
        ld_tx_data  :in  std_logic;
10
        tx_data     :in  std_logic_vector (7 downto 0);
11
        tx_enable   :in  std_logic;
12
        tx_out      :out std_logic;
13
        tx_empty    :out std_logic;
14
        rxclk       :in  std_logic;
15
        uld_rx_data :in  std_logic;
16
        rx_data     :out std_logic_vector (7 downto 0);
17
        rx_enable   :in  std_logic;
18
        rx_in       :in  std_logic;
19
        rx_empty    :out std_logic
20
    );
21
end entity;
22
architecture rtl of uart is
23
    -- Internal Variables
24
    signal tx_reg         :std_logic_vector (7 downto 0);
25
    signal tx_over_run    :std_logic;
26
    signal tx_cnt         :std_logic_vector (3 downto 0);
27
    signal rx_reg         :std_logic_vector (7 downto 0);
28
    signal rx_sample_cnt  :std_logic_vector (3 downto 0);
29
    signal rx_cnt         :std_logic_vector (3 downto 0);
30
    signal rx_frame_err   :std_logic;
31
    signal rx_over_run    :std_logic;
32
    signal rx_d1          :std_logic;
33
    signal rx_d2          :std_logic;
34
    signal rx_busy        :std_logic;
35
    signal rx_is_empty    :std_logic;
36
    signal tx_is_empty    :std_logic;
37
begin
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    -- UART RX Logic
39
    process (rxclk, reset) begin
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        if (reset = '1') then
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            rx_reg        <= (others=>'0');
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            rx_data       <= (others=>'0');
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            rx_sample_cnt <= (others=>'0');
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            rx_cnt        <= (others=>'0');
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            rx_frame_err  <= '0';
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            rx_over_run   <= '0';
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            rx_is_empty   <= '1';
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            rx_d1         <= '1';
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            rx_d2         <= '1';
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            rx_busy       <= '0';
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        elsif (rising_edge(rxclk)) then
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            -- Synchronize the asynch signal
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            rx_d1 <= rx_in;
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            rx_d2 <= rx_d1;
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            -- Uload the rx data
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            if (uld_rx_data = '1') then
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                rx_data  <= rx_reg;
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                rx_is_empty <= '1';
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            end if;
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            -- Receive data only when rx is enabled
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            if (rx_enable = '1') then
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                -- Check if just received start of frame
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                if (rx_busy = '0' and rx_d2 = '0') then
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                    rx_busy       <= '1';
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                    rx_sample_cnt <= X"1";
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                    rx_cnt        <= X"0";
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                end if;
68
                -- Start of frame detected, Proceed with rest of data
69
                if (rx_busy = '1') then
70
                    rx_sample_cnt <= rx_sample_cnt + 1;
71
                    -- Logic to sample at middle of data
72
                    if (rx_sample_cnt = 7) then
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                        if ((rx_d2 = '1') and (rx_cnt = 0)) then
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                            rx_busy <= '0';
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                        else
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                            rx_cnt <= rx_cnt + 1;
77
                            -- Start storing the rx data
78
                            if (rx_cnt > 0 and rx_cnt < 9) then
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                                rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;
80
                            end if;
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                            if (rx_cnt = 9) then
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                                rx_busy <= '0';
83
                                -- Check if End of frame received correctly
84
                                if (rx_d2 = '0') then
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                                    rx_frame_err <= '1';
86
                                else
87
                                    rx_is_empty  <= '0';
88
                                    rx_frame_err <= '0';
89
                                    -- Check if last rx data was not unloaded,
90
                                    if (rx_is_empty = '1') then
91
                                        rx_over_run  <= '0';
92
                                    else
93
                                        rx_over_run  <= '1';
94
                                    end if;
95
                                end if;
96
                            end if;
97
                        end if;
98
                    end if;
99
                end if;
100
            end if;
101
            if (rx_enable = '0') then
102
                rx_busy <= '0';
103
            end if;
104
        end if;
105
    end process;
106
    rx_empty <= rx_is_empty;
107
    
108
    -- UART TX Logic
109
    process (txclk, reset) begin
110
        if (reset = '1') then
111
            tx_reg        <= (others=>'0');
112
            tx_is_empty   <= '1';
113
            tx_over_run   <= '0';
114
            tx_out        <= '1';
115
            tx_cnt        <= (others=>'0');
116
        elsif (rising_edge(txclk)) then
117
118
            if (ld_tx_data = '1') then
119
                if (tx_is_empty = '0') then
120
                    tx_over_run <= '0';
121
                else
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                    tx_reg   <= tx_data;
123
                    tx_is_empty <= '0';
124
                end if;
125
            end if;
126
            if (tx_enable = '1' and tx_is_empty = '0') then
127
                tx_cnt <= tx_cnt + 1;
128
                if (tx_cnt = 0) then
129
                    tx_out <= '0';
130
                end if;
131
                if (tx_cnt > 0 and tx_cnt < 9) then
132
                    tx_out <= tx_reg(conv_integer(tx_cnt) -1);
133
                end if;
134
                if (tx_cnt = 9) then
135
                    tx_out <= '1';
136
                    tx_cnt <= X"0";
137
                    tx_is_empty <= '1';
138
                end if;
139
            end if;
140
            if (tx_enable = '0') then
141
                tx_cnt <= X"0";
142
            end if;
143
        end if;
144
    end process;
145
    tx_empty <= tx_is_empty;
146
147
end architecture;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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Michael Nu wrote:
> I tried to take away all the "tx" rows (transmission) but then i could
> not get pas the test bench.
Why not? Which test bench? Did you get some error messages? Maybe you 
have to adapt the test bench also?

> I tried to take away all the "tx" rows (transmission) but then i could
> not get pas the test bench.
Maybe copy&cut&paste&delete is not enough here. Did you start thinking 
one minute about your homework?

von Michelle N. (nojman)


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Thanks for your reply. I'm new in programing and vhdl and have a hard 
time to understanding and remembering how to procced and solve the task 
we are getting.
I get this error messege on my test bench.


Parsing VHDL file "/nfs/home/neuman/UART2/uart_test2.vhd" into library 
isim_temp
ERROR:HDLCompiler:806 - "/nfs/home/neuman/UART2/uart_test2.vhd" Line 13: 
Syntax error near "<".
ERROR:HDLCompiler:806 - "/nfs/home/neuman/UART2/uart_test2.vhd" Line 22: 
Syntax error near "<".
ERROR:HDLCompiler:806 - "/nfs/home/neuman/UART2/uart_test2.vhd" Line 28: 
Syntax error near "<".


The test bench:

12 -- Component Declaration
13          COMPONENT <component name>
14          PORT(
15                  <port1> : IN std_logic;
16                  <port2> : IN std_logic_vector(3 downto 0);
17                  <port3> : OUT std_logic_vector(3 downto 0)
18                  );
19          END COMPONENT;
20
21          SIGNAL <signal1> :  std_logic;
22          SIGNAL <signal2> :  std_logic_vector(3 downto 0);
23
24
25  BEGIN
26
27  -- Component Instantiation
28          uut: <component name> PORT MAP(
29                  <port1> => <signal1>,
30                  <port3> => <signal2>



I tried to change the "name" to uart but that did not help.
Tell me if you need something more to help me.

von PittyJ (Guest)


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You should read a book about the basics of VHDL. Perhaps the one from 
Peter Ashenden. It contains a chapter about test benches.

von williwilliwallawalla (Guest)


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What you show us is a "template" rather than functional code.

These mysterious "<" and ">" signs delimit the positions where the 
"real" signal and entity names shall be placed by you.

It's sound that you first have to study the language and some example 
code.

von Michelle N. (nojman)


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Thanks for your replies.
My teacher asked me after a hardware course if I wanted to take a course 
where you work with a Basys2 and showed it to me. He asked me if I had 
some programing languish experience and I told him that I only have a 
little bit of Phyton experience, but not much. And know I'm getting this 
hard assignment and just falling more and more behind... :/

But I will get that book from Peter Ashenden you recommended and reed it 
PittyJ :)

I will try to change the names to my signals and my entity name, thanks 
williwilliwallawalla :)

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