comparator in vhdl-ams

sebgimi Guest #3467264
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Hi all! I would like to write a code for a comparator in vhdl-ams. Its 
the first time I use this langage so I'm totally lost... (by the way if 
you know a link with complet lesson on this langage it will be great).

Anyway, I find a simple code on the web, but when I run the entity only, 
the following error is occuring:

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

entity comparator is

--generic (level : Real := 2.5); -- threshold

port(terminal a: electrical; -- analogic in
signal s : out std_logic); -- digital out

end comparator;

This is the error:

port(terminal a: electrical; -- analogic in
|
ncvhdl_p: *E,MISCOL (comparator_ent.vhdl,9|14): expecting a colon (':') 
87[4.3.3] 93[4.3.2].

That seem easy but I compare with others code on the web and I find no 
error. Furthermore I noted that the key word 'terminal' is not in color 
like the others key words. Maybe its a library issue, I don't know...

Can you help please ??
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Lothar M. Moderator (Company: Titel) #3467294
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sebgimi wrote:
> Can you help please ??
Attach your VHDL file (as a *.vhd or a *.vhdl file).
It does not make sense to fiddle around with code snippets...

sebgimi wrote:
> Furthermore I noted that the key word 'terminal' is not in color like
> the others key words. Maybe its a library issue, I don't know...
Its a syntax-highlighting issue of your editor. What toolchain do you 
use?
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sebgimi Guest #3467549
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Thank you for your answer!

I know that just the code of the entity does not make sense, I did that 
to limit the number of errors and to make sure I use the right library 
and syntaxe of vhdl-ams.

The complet code is following:

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entity comparator is 

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generic (level : Real := 2.5); -- threshold

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port( terminal a : in Electrical; -- analogic in

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      signal s : out std_logic);       -- digital out

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end entity comparator; 

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architecture archi of comparator is 

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quantity v across a;       -- across quantity to ground

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begin 

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     s <= `1' when v'Above(level) -- v > level 

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     else `0';                    -- v < level

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end architecture archi;


Now, when I compile the whole code 9 errors are occuring (in 
attachment)...

Do you know from where these errors come and how to fix them?

For information I use ncvhdl/ncsim toolchain.

Thank for your help!
Attached files:
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sebgimi Guest #3467561
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I forgot libraries declaration:

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

Maybe I do not use the right libraries??

And I note that the word 'terminal' is not in color either in my last 
post so it is not an issue from the toolchain I guess.
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Alberto L. Guest #6220036
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Hello Sebastian,
To make an ideal comparator in vhdl-ams is a simple task...

I add here my VHDL-ams code. Then depending if you want to have 
threshold you can comment the last line or not.

You can find the full code on https://miscircuitos.com/ideal-comparator

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library ieee, std;

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use ieee.std_logic_1164.all;

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use ieee.electrical_systems.all;

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entity comparator is    

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    GENERIC(

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        Vthres : REAL := 0.1  --threshold

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    );    

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    PORT(

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        TERMINAL Vin : ELECTRICAL;

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        TERMINAL Vref : ELECTRICAL;

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        result : out std_logic

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    );

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end entity comparator;

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ARCHITECTURE vhdlams of comparator IS 

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      QUANTITY Volt ACROSS Vin TO Vref;

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BEGIN

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    --result &lt;= '1' when (Vin &gt; Vref) else '0'; --without threshold

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    result &lt;= '1' when Volt'above(Vthres) else '0'; --With threshold 

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END vhdlams;

I hope it helps to anyone :)
Regards
Alberto
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