adg712 (switch) in VHDL

sebgimi Guest 2013-12-20 10:48 #3452786

Rate this post

•	▲ useful ▼ not useful

Hi everyone!

I would like to right the code of the component ADG712 (datasheet in 
attachment), but I don't know how to do...

This is my code below (simplified):

entity adg712 is
     port(In1: in std_logic;
          S1: inout std_logic;
          D1: inout std_logic);
end adg712;
architecture archi of adg712 is
     signal out_gate: std_logic;
     out_gate <= not(In1);
     S1 <= out_gate when In1 = '1' else 'z'; -- I think this part
     D1 <= out_gate when In1 = '1' else 'z'; -- is wrong
end archi;


The part I don't understand is the connection between the invert gate 
ouput and the wire S1 and D1.


Can you help me please ?

Attached files:

ADG711_712_713.pdf (253 KB)

Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post

Lothar M. (lkmiller) Moderator (Company: Titel) 2013-12-20 11:01 #3452805

Rate this post

•	▲ useful ▼ not useful

sebgimi wrote:
> The part I don't understand is the connection between the invert gate
> ouput and the wire S1 and D1.
The INx pin of the ADG is a control pin for the behaviour between the 
two switch terminals Sx and Dx. The INx pin determines whether the two 
switch terminals are connected together or they are 'Z'...

> S1 <= out_gate when In1 = '1' else 'z'; -- I think this part
> D1 <= out_gate when In1 = '1' else 'z'; -- is wrong
You are very right.

> Can you help me please ?
Try google with "VHDL zero ohm". Thats a model for a bidirectional 
interconnection between two ports. You just have to tune it up a little 
and involve the control input INx...

Reply Quote Edit Delete Report post

sebgimi Guest 2013-12-20 11:14 #3452823

Rate this post

•	▲ useful ▼ not useful

Thank you for your answer!

So if I understood right, I should write a thing like this:

  S1 <= D1 when In1 = '1' else 'Z';

I never use inout signal, so is this line enough or it will be better 
like this:

         S1 <= D1 when In1 = '1' else 'Z';
         D1 <= S1 when In1 = '1' else 'Z';

Thx

Reply Quote Edit Delete Report post

Lothar M. (lkmiller) Moderator (Company: Titel) 2013-12-20 12:33 #3452963

Rate this post

•	▲ useful ▼ not useful

Try it. Nothing of your proposals will work. It is a little more 
difficult. Thats why I added the search words for google (if you don't 
find anything try to add "Ben Cohen").

Reply Quote Edit Delete Report post

Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Text *

Formatting

[c]C-Code[/c]
[vhdl]VHDL-Code[/vhdl]
[code]code in other languages, ASCII drawings[/code]
[math]formula (LaTeX syntax)[/math]
[[Title]] – link to an article
Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Attachments

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

First name *

Email address *

Not shown to anyone. We send you a link; your post appears once you confirm it there.

Watch this topic

By submitting you create a free account and accept the terms of use.