I would like to right the code of the component ADG712 (datasheet in
attachment), but I don't know how to do...
This is my code below (simplified):
entity adg712 is
port(In1: in std_logic;
S1: inout std_logic;
D1: inout std_logic);
architecture archi of adg712 is
signal out_gate: std_logic;
out_gate <= not(In1);
S1 <= out_gate when In1 = '1' else 'z'; -- I think this part
D1 <= out_gate when In1 = '1' else 'z'; -- is wrong
The part I don't understand is the connection between the invert gate
ouput and the wire S1 and D1.
Can you help me please ?