Hi everyone!
I would like to right the code of the component ADG712 (datasheet in
attachment), but I don't know how to do...
This is my code below (simplified):
1 | entity adg712 is
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2 | port(In1: in std_logic;
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3 | S1: inout std_logic;
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4 | D1: inout std_logic);
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5 | end adg712;
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6 |
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7 | architecture archi of adg712 is
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8 |
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9 | signal out_gate: std_logic;
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10 |
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11 | begin
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12 |
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13 | out_gate <= not(In1);
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14 |
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15 | S1 <= out_gate when In1 = '1' else 'z'; -- I think this part
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16 | D1 <= out_gate when In1 = '1' else 'z'; -- is wrong
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17 |
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18 | end archi;
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The part I don't understand is the connection between the invert gate
ouput and the wire S1 and D1.
Can you help me please ?